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參數(shù)資料
| 型號： | FC80960HT75SL2GT |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| 中文描述： | 32-BIT, 75 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 17/102頁 |
| 文件大?。?/td> | 828K |
| 代理商： | FC80960HT75SL2GT |
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80960HA/HD/HT
Advance Information
Datasheet
11
CLKIN
I
CLOCK INPUT
provides the time base for the 80960Hx. All internal circuitry is
synchronized to CLKIN. All input and output timings are specified relative to
CLKIN.
For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN
frequency by 2. For the 80960HT, the 3x internal clock is derived by multiplying
the CLKIN frequency by 3.
RESET
I
A(L)
RESET
forces the device into reset. RESET causes all external and internal
signals to return to their reset state (if defined). The rising edge of RESET starts
the processor boot sequence.
STEST
I
S(L)
SELF TEST
, when asserted during the rising edge of RESET, causes the
processor to execute its built in self-test.
FAIL
O
H(Q)
B(Q)
R(0)
FAIL
indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL is asserted immediately out of reset and toggles during self-test
to indicate the status of individual tests. If self-test passes, FAIL is de-asserted
and the processor branches to the user’s initialization code. When self-test fails,
the FAIL pin asserts and the processor ceases execution.
ONCE
I
ON-CIRCUIT EMULATION
control: the processor samples this pin during reset. If
it is asserted low at the end of reset, the processor enters ONCE mode. In ONCE
mode, the processor stops all clocks and floats all output pins except the TDO pin.
ONCE uses an internal pull-up resistor; see R
definition in
Table 21 “80960Hx
DC Characteristics” on page 32
. Pull this pin high when not in use.
TCK
I
TEST CLOCK
provides the clocking function for IEEE 1149.1 Boundary Scan
testing.
TDI
I
TEST DATA INPUT
is the serial input pin for IEEE 1149.1 Boundary Scan testing.
TDI uses an internal pull-up resistor; see R
PU
definition in
Table 21 “80960Hx DC
Characteristics” on page 32
.
TDO
O
TEST DATA OUTPUT
is the serial output pin for IEEE 1149.1 Boundary Scan
testing. ONCE does not disable this pin.
TRST
I
TEST RESET
asynchronously resets the Test Access Port (TAP) controller. TRST
must be held low at least 10,000 clock cycles after power-up. One method is to
provide TRST with a separate power-on-reset circuit. TRST includes an internal
pull-up resistor; see R
definition in
Table 21 “80960Hx DC Characteristics” on
page 32
. Pull this pin low when not in use.
TMS
I
TEST MODE SELECT
is sampled at the rising edge of TCK. TCK controls the
sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan
testing. TMS uses an internal pull-up resistor; see R
PU
definition in
Table 21
“80960Hx DC Characteristics” on page 32
.
VCC5
I
5 V REFERENCE VOLTAGE
input is the reference voltage for the 5 V-tolerant I/O
buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When
all inputs are from 3.3 V components, connect this signal to 3.3 V.
VCCPLL
I
PLL VOLTAGE
is the +3.3 VDC analog input for the PLL.
VOLDET
O
VOLTAGE DETECT
signal allows external system logic to distinguish between a
5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active
low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is
available only on the PGA version.
0 = 80960Hx
1 = 80960Cx
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)
Name
Type
Description
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