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參數(shù)資料
| 型號： | FC80960HT60SL2G2 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| 中文描述： | 32-BIT, 60 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | POWER, QUAD, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 81/102頁 |
| 文件大?。?/td> | 828K |
| 代理商： | FC80960HT60SL2G2 |
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80960HA/HD/HT
Advance Information
Datasheet
75
Figure 59. Bus States
Ti = IDLE
Th = HOLD
Ta = ADDRESS
Td = DATA
Tb = BOFF’ed
Taw= address to data wait
Tdw= data to data wait
Tdw= data to address wait
REQUEST= One or more
requests in the bus queue.
READ= The current
access is a read.
WRITE= The current
access is a write.
To = ONCE
Ta
Tb
Td
1
Taw
2
Trw
4
Tdw
3
Th
Ti
To
!BOFF and READ and N
rdd
= 0
and !BLAST or !BOFF and
WRITE and N
wdd
= 0 and !BLAST or
READY!
READ and N
rdd
> 0 or
WRITE and N
wdd
> 0
BOFF
W
d
CNT = 1
!BOFF and
BLAST and
W
a
CNT = 1
W
x
CNT=1 and
HOLD
W
x
CNT > 1
BOFF
!BOFF
HOLD
HOLD
!HOLD
NOTE:
1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as
long as READY and BTERM are de-asserted. When Read Pipelining is enabled, the Ta state of the
subsequent read access is concurrent with the last data cycle of the access. Because External
Ready Control is disabled for Read Pipelining, the address cycle occurs during BLAST.
2. W
a
CNT is decremented during T
aw
3. W
d
CNT is decremented during T
dw
4. W
x
CNT is decremented during T
rw
!HOLD and W
x
CNT=1
and !REQUEST
!HOLD and W
x
CNT=1
and REQUEST
!RESET and
!HOLD and
RESET and
!ONCE
ONCE and
RESET
W
a
CNT > 1
READ and N
rad
> 0 or
WRITE and N
wad
> 0
!BOFF and READ and N
rad
= 0 or
!BOFF and WRITE and N
wad
= 0
!BOFF and READY and !BLAST or
!BOFF and BTERM and !BLAST or !BOFF and
!HOLD and BLAST and REQUEST and N
XDA
= 0
W
d
CNT > 1
KEY:
!BOFF and
HOLD and BLAST
xda
= 0
!BOFF and !HOLD and
BLAST and
and !REQUEST
N
xda
= 0
N
xda
> 0
RESET
BOFF
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