參數(shù)資料
型號: FC80960HD50SL2GM
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
中文描述: 32-BIT, 50 MHz, RISC PROCESSOR, PQFP208
封裝: PLASTIC, QFP-208
文件頁數(shù): 72/102頁
文件大?。?/td> 828K
代理商: FC80960HD50SL2GM
80960HA/HD/HT
66
Advance Information
Datasheet
The processor can stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted).
Depending on the instruction stream and memory wait states, the two signals can be separated by
several CLKIN cycles.
Bus arbitration logic that logically “ANDs” BSTALL and BREQ will not correctly grant the bus to
the processor in all stall cases, potentially degrading processor performance.
Do not logically “AND” BSTALL and BREQ together in arbitration logic. Instead, the simplest
bus arbitration should logically “OR” BSTALL and BREQ to determine the processor’s bus
ownership requirements.
More sophisticated arbitration should recognize the priority nature of these two signals. Using a
traffic light analogy, BREQ is a “yellow light” warning of a possible processor stall and BSTALL
is a “red light” indicating a stall in progress.
Figure 49. BREQ and BSTALL Operation
CLKIN
ADS
BLAST
BREQ
BSTALL
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