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參數資料
| 型號： | FC80960HD50SL2GM |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| 中文描述： | 32-BIT, 50 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 15/102頁 |
| 文件大?。?/td> | 828K |
| 代理商： | FC80960HD50SL2GM |
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80960HA/HD/HT
Advance Information
Datasheet
9
SUP
O
H(Z)
B(Z)
R(1)
SUPERVISOR ACCESS
indicates whether the current bus access originates from
a request issued while in supervisor mode or user mode. SUP can be used by the
memory subsystem to isolate supervisor code and data structures from
non-supervisor access.
0 = Supervisor Mode
1 = User Mode
ADS
O
H(Z)
B(Z)
R(1)
ADDRESS STROBE
indicates a valid address and the start of a new bus access.
ADS is asserted for the first clock of a bus access.
READY
I
S(L)
READY
, when enabled for a memory region, is asserted by the memory
subsystem to indicate the completion of a data transfer. READY is used to
indicate that read data on the bus is valid, or that a write transfer has completed.
READY works in conjunction with the internal wait state generator to
accommodate various memory speeds. READY is sampled after any programmed
wait states:
During each data cycle of a burst access
During the data cycle of a non-burst access
BTERM
I
S(L)
BURST TERMINATE
, when enabled for a memory region, is asserted by the
memory subsystem to terminate a burst access in progress. When BTERM is
asserted, the current burst access is terminated and another address cycle
occurs.
WAIT
O
H(Z)
B(Z)
R(1)
WAIT
indicates the status of the internal wait-state generator. WAIT is asserted
when the internal wait state generator generates N
, N
, N
WDD
and N
RDD
wait states. WAIT can be used to derive a write data strobe.
BLAST
O
H(Z)
B(Z)
R(1)
BURST LAST
indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses after the internal wait-state
generator reaches zero. BLAST remains active as long as wait states are inserted
via the READY pin. BLAST becomes inactive after the final data transfer in a bus
cycle.
DT/R
O
H(Z)
B(Z)
R(0)
DATA TRANSMIT/RECEIVE
indicates direction for data transceivers. DT/R is
used with DEN to provide control for data transceivers connected to the data bus.
DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is
driven high when the processor is “transmitting” data (a store cycle). DT/R only
changes state when DEN is high.
0 = Data Receive
1 = Data Transmit
DEN
O
H(Z)
B(Z)
R(1)
DATA ENABLE
indicates data transfer cycles during a bus access. DEN is
asserted at the start of the first data cycle in a bus access and de-asserted at the
end of the last data cycle. DEN remains asserted for an entire bus request, even
when that request spans several bus accesses. For example, a ldq instruction
starting at an unaligned quad word boundary is one bus request spanning at least
two bus accesses. DEN remains asserted throughout all the accesses (including
ADS states) and de-asserts when the Iqd instruction request is satisfied. DEN is
used with DT/R to provide control for data transceivers connected to the data bus.
DEN remains asserted for sequential reads from pipelined memory regions.
LOCK
O
H(Z)
B(Z)
R(1)
BUS LOCK
indicates that an atomic read-modify-write operation is in progress.
LOCK may be used by the memory subsystem to prevent external agents from
accessing memory that is currently involved in an atomic operation (e.g., a
semaphore). LOCK is asserted in the first clock of an atomic operation and
de-asserted when BLAST is deasserted in the last bus cycle.
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)
Name
Type
Description
相關PDF資料 |
PDF描述 |
|---|---|
| FC80960HD66SL2GN | AC 3C 3#16S PIN RECP |
| FC80960HD80SL2LZ | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| FC80960HT60SL2G2 | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| FC80960HT75SL2GT | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| FC80960HA25SL2GU | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| FC80960HD66SL2GN | 功能描述:IC MPU I960HD 3V 66MHZ 208-SQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| FC80960HD80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FC80960HD80SL2LZ | 功能描述:IC I960HD 3.3V 80MHZ 208QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應商設備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| FC80960HT60SL2G2 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| FC80960HT75 S L2GT | 制造商:Intel 功能描述:MPU i960? Processor RISC 32-Bit 75MHz 208-Pin PQFP |
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