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參數(shù)資料
| 型號： | FAB2210UCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 7/26頁 |
| 文件大小： | 0K |
| 描述： | IC SUBSYSTEM HDPH AMP G 20-WLCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | D 類；G 類 |
| 輸出類型： | 1-通道（單聲道），帶立體聲耳機 |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 3.3W x 1 @ 8 歐姆; 29mW x 2 @ 32 歐姆 |
| 電源電壓： | 2.8 V ~ 5.25 V |
| 特點： | 消除爆音，差分輸入，I²C，靜音，短路和熱保護，關(guān)機，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 20-WLCSP |
| 封裝/外殼： | 20-UFBGA，WLCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FAB2210UCXFSDKR |
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23
9614A–AT42–08/10
AT42QT2161
If the host sends more than one data byte, they will be written to consecutive memory
addresses. The device automatically increments the target memory address after writing each
data byte. After writing the last data byte, the host should send the STOP condition.
The host should not try to write beyond address 255 because the device will not increment the
internal memory address beyond this.
5.3.2
Reading Data From the Device
The sequence of events required to read data from the device is shown next.
The host initiates the transfer by sending the START condition, and follows this by sending the
slave address of the device together with the Write-bit. The device sends an ACK. The host then
sends the memory address within the device it wishes to read from. The device sends an ACK.
The host must then send a STOP and a START condition followed by the slave address again
but this time accompanied by the Read-bit. The device will return an ACK, followed by a data
byte. The host must return either an ACK or NACK. If the host returns an ACK, the device will
subsequently transmit the data byte from the next address. Each time a data byte is transmitted,
the device automatically increments the internal address. The device will continue to return data
bytes until the host responds with a NACK. The host should terminate the transfer by issuing the
STOP condition.
5.4
SDA, SCL
The I2C-compatible bus transmits data and clock with SDA and SCL. They are open-drain; that is
I2C
-compatible master and slave devices can only drive these lines low or leave them open. The
termination resistors (Rp) pull the line up to Vdd if no I2C-compatible device is pulling it down.
The termination resistors commonly range from 1 k
to 10 kand should be chosen so that the
rise times on SDA and SCL meet the I
2C-compatible specifications (1s maximum).
5.5
CHANGE Pin
The CHANGE pin is an active low open drain output that can be used to alert the host of any
changes to any of the 5 status bytes (address 2 to 6), thus reducing the need for wasteful
I2C
-compatible communications. After setting up the QT2161, the host can simply not
communicate with the device, except when the CHANGE pin goes active.
CHANGE goes inactive again only when the host performs a read from all status bytes which
have changed.
Poll rate: The host can make use of the CHANGE pin output to initiate a communication; this will
guarantee the optimal polling rate.
If the host cannot make use of the CHANGE pin, the poll rate should be no faster than once per
matrix scan (see Section 9.4 on page 45). Anything faster will not provide new information and
will slow down the chip operation.
The CHANGE pin requires a pull-up resistor, with a typical value of ~100 k
.
SLA+W
MemAddress
AA
S
SLA+R
A
P
Host to Device
Device to Host
P
A
/A
Data 1
Data 2
Data n
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