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參數(shù)資料
| 型號： | FAB2210UCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SUBSYSTEM HDPH AMP G 20-WLCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | D 類；G 類 |
| 輸出類型： | 1-通道（單聲道），帶立體聲耳機(jī) |
| 在某負(fù)載時最大輸出功率 x 通道數(shù)量： | 3.3W x 1 @ 8 歐姆; 29mW x 2 @ 32 歐姆 |
| 電源電壓： | 2.8 V ~ 5.25 V |
| 特點(diǎn)： | 消除爆音，差分輸入，I²C，靜音，短路和熱保護(hù)，關(guān)機(jī)，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 20-WLCSP |
| 封裝/外殼： | 20-UFBGA，WLCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FAB2210UCXFSDKR |
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2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAB2210 Rev. 1.1.2
7
FAB2210
—
Audio
Subsystem
with
Class-G
Headphone
and
3.3W
Mono
Clas
s-D
Speaker
with
Dyna
mic
Range
Compressi
on
I2C DC Electrical Characteristics
Unless otherwise noted, SVDD=2.8 V to 5.25 V, DVDD=1.6 V to 2.8 V, TA=-40°C to 85°C.
Symbol
Parameter
Fast Mode (400 kHz)
Min.
Max.
Unit
VIL
Low-Level Input Voltage
-0.3
0.6
V
VIH
High-Level Input Voltage
1.3
V
VOL
Low-Level Output Voltage at 3 mA Sink Current
(Open-Drain or Open-Collector)
0
0.4
V
IIH
High-Level Input Current of Each I/O Pin, Input Voltage=VSVDD
-1
1
A
IIL
Low-Level Input Current of Each I/O Pin, Input Voltage=0V
-1
1
A
I2C AC Electrical Characteristics
Unless otherwise noted, SVDD=2.8 V to 5.25 V, DVDD=1.6 V to 2.8 V, TA=-40°C to 85°C.
Symbol
Parameter
Fast Mode (400 kHz)
Min.
Max.
Unit
fSCL
SCL Clock Frequency
0
400
kHz
tHD;STA
Hold Time (Repeated) START Condition
0.6
s
tLOW
Low Period of SCL Clock
1.3
s
tHIGH
High Period of SCL Clock
0.6
s
tSU;STA
Set-up Time for Repeated START Condition
0.6
s
tHD;DAT
Data Hold Time
0
0.9
s
tSU;DAT
Data Set-up Time
(4)
100
ns
tr
Rise Time of SDA and SCL Signals
(5)
20+0.1Cb
300
ns
tf
Fall Time of SDA and SCL Signals
(5)
20+0.1Cb
300
ns
tSU;STO
Set-up Time for STOP Condition
0.6
s
tBUF
Bus-Free Time between STOP and START Conditions
1.3
s
tSP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
50
ns
Notes:
4.
A Fast-Mode I
2C Bus device can be used in a Standard-Mode I2C Bus system, but the requirement tSU;DAT
≥
250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
Serial Data (SDA) line tr_max + tSU;DAT=1000 + 250=1250 ns (according to the Standard-Mode I
2C Bus
specification) before the SCL line is released.
5.
Cb equals the total capacitance of one bus line in pf. If mixed with High-Speed Mode devices, faster fall times are
allowed according to the I
2C specification.
Figure 3. Definition of Timing for Full-Speed Mode Devices on the I
2C Bus
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