參數(shù)資料
型號: FAB2210UCX
廠商: Fairchild Semiconductor
文件頁數(shù): 19/26頁
文件大小: 0K
描述: IC SUBSYSTEM HDPH AMP G 20-WLCSP
標準包裝: 1
類型: D 類;G 類
輸出類型: 1-通道(單聲道),帶立體聲耳機
在某負載時最大輸出功率 x 通道數(shù)量: 3.3W x 1 @ 8 歐姆; 29mW x 2 @ 32 歐姆
電源電壓: 2.8 V ~ 5.25 V
特點: 消除爆音,差分輸入,I²C,靜音,短路和熱保護,關(guān)機,音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 20-WLCSP
封裝/外殼: 20-UFBGA,WLCSP
包裝: 標準包裝
其它名稱: FAB2210UCXFSDKR
34
9614A–AT42–08/10
AT42QT2161
The burst length is the number of times the charge-transfer (QT) process is performed on a
given key. Each QT process is simply the pulsing of an X line once, with a corresponding Y line
enabled to capture the resulting charge passed through the key’s capacitance Cx.
Increasing burst length directly affects key sensitivity. This occurs because the accumulation of
charge in the charge integrator is directly linked to the burst length. The burst length of each key
can be set individually, allowing for direct digital control over the signal gains of each key
individually.
Apparent touch sensitivity is also controlled by the Negative Threshold level (NTHR). Burst
length and NTHR interact; normally burst lengths should be kept as short as possible to reduce
scan time and limit RF emissions, but NTHR should be kept above 6 to reduce false detections
due to external noise. The detection integrator mechanism also helps to prevent false
detections.
Note: setting a burst length of zero for a specific key, disables that key.
Typical values: 8 to 32 (32 to 128 burst pulses)
Default: 4 (16 burst pulses)
6.22
Address 70 – 71: GPIO/GPO Drive
If the GPIOs are set to outputs, the drive for the individual GPIO is set according to the
corresponding bit in GPIO Drive bytes. Setting the bit to 1 will drive the corresponding GPIO pin
to Vdd, while setting it to 0, will drive the corresponding GPIO pin to ground.
Enabling PWM on a GPIO pin will override the drive on the pin.
Shared X line GPOs will be only driven when not doing any measurements. During
measurements, burst pulses will be driven from the X lines, make sure that the driven device will
not be affected.
Default: 0 (All driven low)
6.23
Address 73: GPIO Direction
Sets the direction of the GPIOs: 1 = driven outputs, 0 = floating inputs.
If set as inputs, the GPIO will only be read every 16 ms (fixed cycle time).
Table 6-23.
GPIO/GPO Drive
Address
b7b6b5
b4b3b2b1
b0
70
X7
X6
X5
X4
X3
X2
X1
X0
71
0
GPIO3
GPIO2
GPIO1
0
Table 6-24.
GPIO Direction
Address
b7b6b5
b4b3b2b1
b0
73
0
GPIO3
GPIO2
GPIO1
0
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