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參數(shù)資料
型號(hào): FAB2200UCX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 8/18頁(yè)
文件大小: 0K
描述: IC SUBSYSTEM HDPH AMP G 25-WLCSP
標(biāo)準(zhǔn)包裝: 1
類型: D 類;G 類
輸出類型: 1-通道(單聲道),帶立體聲耳機(jī)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 1.2W x 1 @ 8 歐姆; 41mW x 2 @ 32 歐姆
電源電壓: 2.8 V ~ 5.25 V
特點(diǎn): 消除爆音,差分輸入,I²C,靜音,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 25-WLCSP
封裝/外殼: 25-UFBGA,WLCSP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: FAB2200UCXFSDKR
16
COMMERCIALTEMPERATURERANGE
IDT72V70180 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 128 x 128
tALW
ADDRESS
DATA
tADS
tADH
ALE
5716 drw11
tRW
tWW
tCSRW
tALRD
tCSR
tCSW
tDHW
tDHR
tAKH
tDDR
tDSW
tSWD
tALWR
tAKD
AD0-AD7
D8-D15
CS
RD
WR
DTA
Figure 11. Multiplexed Bus Timing (Intel Mode)
AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL)
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with R
L, with timing corrected to cancel time taken to discharge CL.
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
tALW
ALE Pulse Width
20
ns
tADS
Address Setup from ALE falling
3
ns
tADH
Address Hold from ALE falling
3
ns
tALRD
RD Active after ALE falling
3
ns
tDDR
Data Setup from
DTA LOW on Read
5
ns
CL = 150pF
tCSRW
CS Hold after RD/WR
5ns
tRW
RD Pulse Width (Fast Read)
45
ns
tCSR
CS Setup from RD
0ns
tDHR(1)
Data Hold after
RD
10
20
ns
CL = 150pF, RL = 1K
tWW
WR Pulse Width (Fast Write)
45
ns
tALWR
WR Delay after ALE falling
3
ns
tCSW
CS Setup from WR
0ns
tDSW
Data Setup from
WR (FastWrite)
20
ns
tSWD
Valid Data Delay on Write (Slow Write)
122
ns
tDHW
Data Hold after
WR Inactive
5
ns
tAKD
Acknowledgment Delay:
Reading/WritingRegisters
43/43
ns
CL = 150pF
Reading/Writing Memory
760/750
ns
CL = 150pF
tAKH(1)
Acknowledgment Hold Time
22
ns
CL = 150pF, RL = 1K
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