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參數(shù)資料
| 型號(hào)： | FAB2200UCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SUBSYSTEM HDPH AMP G 25-WLCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | D 類；G 類 |
| 輸出類型： | 1-通道（單聲道），帶立體聲耳機(jī) |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 1.2W x 1 @ 8 歐姆; 41mW x 2 @ 32 歐姆 |
| 電源電壓： | 2.8 V ~ 5.25 V |
| 特點(diǎn)： | 消除爆音，差分輸入，I²C，靜音，短路和熱保護(hù)，關(guān)機(jī)，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 25-WLCSP |
| 封裝/外殼： | 25-UFBGA，WLCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FAB2200UCXFSDKR |
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6
COMMERCIALTEMPERATURERANGE
IDT72V70180 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 128 x 128
Connection Memory
10000001
10000010
Data Memory
0
1
0
2
1
3
Stream
Control Register
CRb7
5716 drw03
10000000
The Control Register is only accessed when A7-A0
are all zeroed. When A7 =1, up to 32 bytes are
randomly accessable via A0-A4 at any one instant.
Of which stream these bytes (channels) are accessed
is determined by the state of CRb1 -CRb0.
CRb6CRb5CRb4CRb3CRb2CRb1CRb0
CRb1CRb0
0
1
CRb4
10011111
External Address Bits A7-A0
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 0
Channel 1
Channel 2
Channel 31
Figure 3. Addressing Internal Memories
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V70180
After power up, the state of the connection memory is unknown. As such,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
CONNECTION MEMORY CONTROL
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 4 for detail.
Theprocessorchannel(PC)bitoftheconnectionmemoryselectsbetween
Processor Mode and Connection Mode. If high, the contents of the connection
memoryareoutputontheTXstreams. Iflow,thestreamaddressbit(SAB)and
the channel address bit (CAB) of the connection memory defines the source
information(streamandchannel)ofthetime-slotthatwillbeswitchedtotheoutput
from data memory.
The
V/C(Variable/ConstantDelay)bitineachconnectionmemorylocation
allows the per-channel selection between variable and constant throughput
delay modes.
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