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參數(shù)資料
| 型號： | FA5502 |
| 廠商： | FUJI ELECTRIC HOLDINGS CO., LTD. |
| 英文描述： | POWER SUPPLY CONTROL IC |
| 中文描述： | 電源控制IC |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 215K |
| 代理商： | FA5502 |
(2) Voltage error amplifier and overvoltage
limiting circuit
ER.AMP is an error amplifier which constitutes a
voltage feedback loop for keeping the output voltage
constant.
The
non-inverting
connected to reference voltage Vr of 1.55V (typ.).
Fig.6 shows the connection. The output voltage is
determined by:
14
Quality is our message
(3) Current error amplifier and overcurrent
limiter circuit
CUR.AMP is an error amplifier which constitutes a
current loop to control the line current to a sinusoidal
waveform. As shown in Fig.7, to IIN- pin (pin 2), a
multiplier output is connected via resistor RA as a
current reference signal. Inductor current is monitored
by IDET pin (pin 16). The IDET pin should be used
within the voltage range from 0V to –1.0V in normal
operation. RC network for loop compensation is
connected between IFB pin and IIN- pin. According to
the circuit in Fig.7, the characteristics of voltage gain
AV are as shown in Fig.8. Where,
FA5502P/M
input
is
internally
Vr
1
R
2
R
1
R
V
O
×
+
=
(1)
The error amplifier output is pinned out at VFB pin
(pin 5). Between VFB pin and VIN- pin, RC network
are connected for loop compensation. The voltage
gain Av is expressed by
(
)
4
R
1
C
j
1
3
R
4
R
ω
A
V
×
+
=
(2)
Cutoff frequency fc is expressed by:
4
R
1
C
2
1
f
C
×
π
=
(3)
If 100Hz or 120Hz ripples appear at the error
amplifier output, the PFC converter will not operate
stably. Therefore, determine C1 and R4 so that voltage
gain Av at 100 Hz or 120 Hz will be small enough. Also
set fc to approximately 1Hz to ensure a stable
operation. Practically, the optimum value should be
determined by evaluation in the actual circuit.
To limit the output voltage when it has risen above
the normal voltage, overvoltage limiting comparator
OVP.COMP is incorporated. Its threshold voltage Vp is
as follows:
Vr
V
P
×
α
=
(
α
=1.058(typ)) (4)
According to the connection in Fig.6, therefore, the
output overvoltage is limited to 1.058 times (typ.) the
normal output voltage.
5
6
4
Vo
VFB
VIN-
OVP
R4
C1
R3
R2
R1
MUL
F.F.
Vr
=1.55V(typ.)
Vp
=1.058Vr(typ.)
ER.AMP
OVP.COMP
Fig.6 Voltage error amplifier and overvoltage limiting
circuit
3
C
5
R
2
1
Z
×
π
=
(5)
C
5
R
2
1
P
×
π
=
3
C
2
C
3
C
2
C
C
+
×
=
(6)
Voltage gain (G1) between Z and P (gain between
IDET pin and IFB pin) in Fig.8 is:
+
=
1
RA
5
R
75
.
log
20
1
G
(7)
Select C2 and C3 so that P/Z will be about 10 for
adequate phase margin. The output of current error
amplifier is input to PWM comparator.
The optimum value of loop compensation should be
determined by evaluation in actual circuit referring to
application circuit, etc.
To limit the overcurrent, overcurrent limiting
comparator OCP.COMP is provided. The threshold
voltage at IDET pin is -1.10V (typ.). If a noise is picked
up at IDET pin, suppress it by connecting Rn and Cn.
Rn must be lower than 27
.
1
2
16
IFB
IIN-
IDET
R5
C2
C3
PWM
comparator
F.F.
0.39V
MUL
RC
RB
4.85k
15k
REF
5V
RA
11k
Cn
Rn
currnet
detection
CUR.AMP
OCP.COMP
Vm
Fig.7 Current error amplifier and overcurrent limiting
circuit
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