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參數(shù)資料
| 型號(hào)： | EVAL-CN0217-EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR CN0217 |
| 設(shè)計(jì)資源： | CN-0217 Circuit Eval Board |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Circuits from the Lab™ |
| 主要目的： | 阻抗轉(zhuǎn)換器 |
| 已用 IC / 零件： | AD5933，AD5934，AD8606 |
| 主要屬性： | 網(wǎng)絡(luò)分析器 |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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Data Sheet
AD5933
Rev. E | Page 13 of 40
SYSTEM DESCRIPTION
ADC
(12 BITS)
VDD/2
DDS
CORE
(27 BITS)
DAC
Z(ω)
I2C
INTERFACE
IMAGINARY
REGISTER
REAL
REGISTER
MAC CORE
(1024 DFT)
LPF
SCL
SDA
MCLK
ROUT
VOUT
AD5933
RFB
VIN
PROGRAMMABLE
GAIN AMPLIFIER
×5
×1
WINDOWING
OF DATA
COS
SIN
MICROCONTROLLER
MCLK
05324-
017
TEMPERATURE
SENSOR
OSCILLATOR
Figure 17. Block Overview
The AD5933 is a high precision impedance converter system
solution that combines an on-board frequency generator with a
12-bit, 1 MSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase are easily calculated using the following equations:
2
I
R
Magnitude
+
=
Phase = tan1(I/R)
To characterize an impedance profile Z(ω), generally a frequency
sweep is required, like that shown in Figure 18.
FREQUENCY
IM
P
E
DANCE
05324-
018
Figure 18. Impedance vs. Frequency Profile
The AD5933 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 5 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range for 3.3 V. These
values are ratiometric with VDD. So for a 5 V supply
p
V
3
.
3
0
.
5
98
.
1
=
×
=
1
Range
for
Voltage
Excitation
Output
p
V
24
.
2
3
.
3
0
.
5
48
.
1
=
×
=
1
Range
for
Voltage
Bias
DC
Output
Table 5. Voltage Levels Respective Bias Levels for 3.3 V
Range
Output Excitation
Voltage Amplitude
Output DC Bias Level
1
1.98 V p-p
1.48 V
2
0.97 V p-p
0.76 V
3
383 mV p-p
0.31 V
4
198 mV p-p
0.173 V
The excitation signal for the transmit stage is provided on-chip
using DDS techniques that permit subhertz resolution. The receive
stage receives the input signal current from the unknown impedance,
performs signal processing, and digitizes the result. The clock for
the DDS is generated from either an external reference clock,
which is provided by the user at MCLK, or by the internal
oscillator. The clock for the DDS is determined by the status of
Bit D3 in the control register (see Register Address 0x81 in the
Register Map section).
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