參數(shù)資料
型號： EVAL-ADV7179EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 2/52頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADV7179
設計資源： ADV7174/79 Eval Brd Docs
標準包裝： 1
主要目的： 視頻，視頻處理
嵌入式： 否
已用 IC / 零件： ADV7179
主要屬性： NTSC/PAL 數(shù)字視頻編碼器
次要屬性： I²C 接口
已供物品： 板
ADV7174/ADV7179
Rev. B | Page 10 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
37
36
35
38
39
40
33
32
31
34
11
12
13
14
15
16
17
18
19
20
3
4
5
6
7
1
2
10
8
9
26
27
28
29
24
25
22
23
21
30 VREF
DAC A
DAC B
VAA
GND
VAA
DAC C
BLANK
GND
H
SYN
C
FIELD
/VSYN
C
ALS
B
CLOCK
VAA
P5
P6
P7
GND
VAA
COMP
SDATA
SCLOCK
GND
V
AA
GND
R
ESET
GND
P4
P3
P2
P1
P0
TTX
TTXREQ
R
SET
SC
R
ESET/
RTC
PIN 1
INDICATOR
ADV7174/ADV7179
LFCSP
TOP VIEW
(Not to Scale)
02980-A
-005
Figure 5. Pin Configurations
Table 6. Pin Function Descriptions
Mnemonic
Input/
Output
Function
P7–P0
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0). P0 is the LSB.
CLOCK
I
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz
(NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC
I/O
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (master mode) or accept (slave
mode) sync signals.
FIELD/VSYNC
I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output
(master mode) or accept (slave mode) these control signals.
BLANK
I/O
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.
SCRESET/RTC
I
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a
subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0.
Alternatively, it can be configured as a real-time control (RTC) input.
VREF
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
RSET
I
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals.
COMP
O
Compensation Pin. Connect a 0.1 μF capacitor from COMP to VAA. For optimum dynamic performance in low
power mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF.
DAC A
O
DAC Output (see Table 13)
DAC B
O
DAC Output (see Table 13).
DAC C
O
DAC Output (see Table 13).
SCLOCK
I
MPU Port Serial Interface Clock Input.
SDATA
I/O
MPU Port Serial Data Input/Output.
ALSB
I
TTL Address Input. This signal sets up the LSB of the MPU address.
RESET
I
This input resets the on-chip timing generator and sets the ADV7174/ADV7179 into default mode. This is NTSC
operation, Timing Slave Mode 0, 8-bit operation, 2× composite out signals. DACs A, B, and C are enabled.
TTX
I
Teletext Data.
TTXREQ
O
Teletext Data Request Signal/Defaults to GND when Teletext Not Selected.
VAA
P
Power Supply (2.8 V or 3.3 V).
GND
G
Ground Pin.
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