- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17112 > EVAL-ADUC831QSZ (Analog Devices Inc)KIT DEV FOR ADUC831 QUICK START PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADUC831QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 39/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC831 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC831 |
| 所含物品： | 評估板、電源、纜線、軟件和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADUC831BCPZ-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP ADUC831BCPZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP ADUC831BSZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 52MQFP ADUC831BSZ-ND - IC ADC/DAC 12BIT W/MCU 52-MQFP |
| 其它名稱： | EVAL-ADUC831QS EVAL-ADUC831QS-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
REV. 0
–44–
ADuC831
WDCON
Watchdog Timer Control Register
SFR Address
C0H
Power-On Default Value
10H
Bit Addressable
Yes
Table XV. WDCON SFR Bit Designations
Bit
Name
Description
7
PRE3
Watchdog Timer Prescale Bits.
6
PRE2
The Watchdog timeout period is given by the equation: tWD = (2
PRE
(2
9/f
R/C OSC))
5
PRE1
(0
≤ PRE ≤ 7; f
R/C OSC = 32 kHz
10% at 25C)
4
PRE0
PRE3 PRE2 PRE1
PRE0 Timeout Period (ms) Action
000
0
15.6
Reset or Interrupt
000
1
31.2
Reset or Interrupt
001
0
62.5
Reset or Interrupt
001
1
125
Reset or Interrupt
010
0
250
Reset or Interrupt
010
1
500
Reset or Interrupt
011
0
1000
Reset or Interrupt
011
1
2000
Reset or Interrupt
100
0
0.0
Immediate Reset
PRE3–0 > 1000
Reserved
3
WDIR
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog will generate an interrupt response instead of a
system reset when the watchdog timeout period has expired. This interrupt is not disabled by
the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not
being used to monitor the system, it can alternatively be used as a timer. The prescaler is used
to set the timeout period in which an interrupt will be generated.
2
WDS
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.
1
WDE
Watchdog Enable Bit.
Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user
within the watch dog timeout period, the watchdog will generate a reset or interrupt, depending
on WDIR. Cleared under the following conditions, user writes “0,” Watchdog Reset (WDIR = “0”);
Hardware Reset; PSM Interrupt.
0
WDWR
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit
must be set and the very next instruction must be a write instruction to the WDCON SFR.
For example:
CLR
EA
;disable interrupts while writing
;to WDT
SETB WDWR
;allow write to WDCON
MOV
WDCON, #72H ;enable WDT for 2.0s timeout
SETB EA
;enable interrupts again (if rqd)
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device
reset or interrupt within a reasonable amount of time if the
ADuC831 enters an erroneous state, possibly due to a program-
ming error or electrical noise. The watchdog function can be
disabled by clearing the WDE (Watchdog Enable) bit in the
Watchdog Control (WDCON) SFR. When enabled, the watch-
dog circuit will generate a system reset or interrupt (WDS) if
the user program fails to set the watchdog (WDE) bit within a
predetermined amount of time (see PRE3–0 bits in WDCON).
The watchdog timer itself is a 16-bit counter that is clocked at
32 kHz by the internal R/C oscillator. The watchdog time out
interval can be adjusted via the PRE3–0 bits in WDCON. Full
control and status of the watchdog timer function can be con-
trolled via the watchdog timer control SFR (WDCON). The
WDCON SFR can only be written by user software if the
double write sequence described in WDWR below is initiated
on every write access to the WDCON SFR.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMM08DRKI | CONN EDGECARD 16POS DIP .156 SLD |
| 0210490856 | CABLE JUMPER 1.25MM .051M 17POS |
| EVAL-ADUC7028QSZ | KIT DEV ADUC7028 QUICK START |
| GMM12DREN | CONN EDGECARD 24POS .156 EYELET |
| GSM12DREH | CONN EDGECARD 24POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC832QS | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk 制造商:Analog Devices 功能描述:DEVELOPMENT KIT SYSTEM |
| EVAL-ADUC832QSZ | 功能描述:KIT DEV FOR ADUC832 QUICK START RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| EVAL-ADUC834QS | 制造商:Analog Devices 功能描述:DATA ACQ SYS, MICROCNVRTR, DUAL 16BIT/24BIT - ADCS W/ EMBEDD - Bulk 制造商:Analog Devices 功能描述:8052 ADUC834 QUICKSTART DEV KIT |
| EVAL-ADUC834QSZ | 功能描述:KIT DEV QUICK START ADUC834 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| EVAL-ADUC836QS | 制造商:Analog Devices 功能描述:MCU 8BIT 8052 CISC 62KB+4KB FLASH 3.6V 48LQFP - Bulk 制造商:Analog Devices 功能描述:KIT- ADUC836 DEV SYSTEM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。