參數(shù)資料
型號(hào)： EVAL-ADUC7023QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 86/96頁
文件大?。?/td> 0K
描述： KIT DEV FOR ADUC7023 QUICK START
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： ARM7TDMI
所含物品： 板
Data Sheet
ADuC7023
| Page 87 of 96
T2CLRI Register
Name:
T2CLRI
Address:
0xFFFF036C
Default value:
0xXX
Access:
Write
T2CLRI is an 8-bit register. Writing any value to this register on
successive occassions clears the Timer2 interrupt in normal
mode or resets a new timeout period in watchdog mode.
The user must perform successive writes to this register to ensure
resetting the timeout period.
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T2CLRI
to avoid a watchdog reset. The value is a sequence generated by
the 8-bit linear feedback shift register (LFSR) polynomial = X8
+ X6 + X5 + X + 1 shown in Figure 45.
The initial value or seed is written to T2CLRI before entering
watchdog mode. After entering watchdog mode, a write to T2CLRI
must match this expected value. If it matches, the LFSR is advanced
to the next state when the counter reload happens. If it fails to
match the expected state, a reset is immediately generated, even
if the count has not yet expired.
The value 0x00 should not be used as an initial seed due to the
properties of the polynomial. The value 0x00 is always guaranteed
to force an immediate reset. The value of the LFSR cannot be
read; it must be tracked/generated in software.
An example of a sequence follows:
1.
Enter initial seed, 0xAA, in T2CLRI before starting Timer2
in watchdog mode.
2.
Enter 0xAA in T2CLRI; Timer2 is reloaded.
3.
Enter 0x37 in T2CLRI; Timer2 is reloaded.
4.
Enter 0x6E in T2CLRI; Timer2 is reloaded.
5.
Enter 0x66. 0xDC was expected; the watchdog resets the chip.
08675-
039
CLOCK
Q
D
4
Q
D
5
Q
D
3
Q
D
7
Q
D
6
Q
D
2
Q
D
1
Q
D
0
Figure 45. 8-Bit LFSR
Rev. E
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