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參數資料
| 型號： | EVAL-ADF4360-6EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 22/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4360-6 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-6 |
| 主要屬性： | 帶 VCO 的單路整數-N PLL |
| 次要屬性： | 1.15GHz，200kHz PFD |
| 已供物品： | 板，線纜，軟件 |
| 相關產品： | ADF4360-6BCPZ-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-6BCPZRL7-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-6BCPZRL-ND - IC SYNTHESIZER VCO 24LFCSP |
Data Sheet
ADF4360-6
Rev. B | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04440-
003
ADF4360-6
TOP VIEW
(Not to Scale)
CPGND
1
AVDD 2
AGND
3
RFOUTA 4
RFOUTB 5
VVCO 6
DATA
18
CLK
17
REFIN
16
DGND
15
CN
14
RSET
13
V
T
UNE
7
AG
ND
8
AG
ND
9
AG
ND
10
AG
ND
11
C
12
CP
24
CE
23
AG
ND
22
DV
DD
21
M
UX
O
UT
20
LE
19
PIN 1
IDENTIFIER
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 3. Pin Configuration
Table 4. Pin Functional Descriptions
Pin No.
Mnemonic
Description
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2
AVDD
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must have the same value as DVDD.
3, 8 to 11, 22
AGND
Analog Ground. This is the ground return path of the prescaler and VCO.
4
RFOUTA
VCO Output. The output level is programmable from 4.5 dBm to 13.5 dBm. See the Output Matching section
for a description of the various output stages.
5
RFOUTB
VCO Complementary Output. The output level is programmable from 4.5 dBm to 13.5 dBm. See the Output
Matching section for a description of the various output stages.
6
VVCO
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. VVCO must have the same value as AVDD.
7
VTUNE
Control Input to the VCO. This voltage determines the output frequencyand is derived from filtering the CP output voltage.
12
CC
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the syn-
thesizer. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
SET
CPmax
R
I
75
.
11
=
Where RSET = 4.7 k, ICPmax = 2.5 mA.
14
CN
Internal Compensation Node. This pin must be decoupled to VVCO with a 10 F capacitor.
15
DGND
Digital Ground.
16
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 k. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
21
DVDD
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD must have the same value as AVDD.
23
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
Taking the pin high powers up the device depending on the status of the power-down bits.
24
CP
Charge Pump Output. When enabled, this provides ± ICP to the external loop filter, which in turn drives the internal VCO.
EP
Exposed Pad. The exposed pad must be connected to AGND.
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