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參數(shù)資料
| 型號： | EVAL-ADF4157EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4157 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4157 |
| 主要屬性： | 單路分?jǐn)?shù)-N PLL |
| 次要屬性： | 6GHz |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADF4157BRUZ-ND - IC PLL FREQ SYNTH 6GHZ 16TSSOP ADF4157BRUZ-RL7-ND - IC PLL FREQ SYNTH 6GHZ 16TSSOP ADF4157BRUZ-RL-ND - IC PLL FREQ SYNTH 6GHZ 16TSSOP |
ADF4157
Data Sheet
Rev. D | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
CPGND
AGND
AVDD
RFINA
RFINB
RSET
DVDD
MUXOUT
LE
CE
REFIN
DGND
CLK
DATA
VP
ADF4157
TOP VIEW
(Not to Scale)
05
87
4-
00
3
Figure 3. TSSOP Pin Configuration
0
587
4-
00
4
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE THERMALLY CONNECTED TO A COPPER
PLANE FOR ENHANCED THERMAL PERFORMANCE.
THIS PAD SHOULD BE CONNECTED TO AGND.
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11 CE
CPGND
AGND
2
AGND
RFINB
5
RFINA
7
A
V
D
6
A
V
D
8
R
E
F
IN
9
D
G
N
D
1
0
D
G
N
D
1
9
R
S
E
T
2
0
C
P
1
8
V
P
1
7
D
V
D
1
6
D
V
D
ADF4157
TOP VIEW
(Not to Scale)
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic
Description
1
19
RSET
Connecting a resistor between this pin and ground sets the maximum charge pump output
current.
The relationship between ICP and RSET is
SET
CPMAX
R
I
5
.
25
where:
RSET = 5.1 kΩ.
I= 5 mA.
2
20
CP
Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which, in
turn, drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF.
6
5
RFINA
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7
6, 7
AVDD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have
the same voltage as DVDD.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it
can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the input shift register on the CLK rising edge. This input is a high impedance
CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
This input is a high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE is high, the data stored in the input shift register is loaded
into one of the five latches, with the latch selected using the control bits.
14
15
MUXOUT
This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
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