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參數(shù)資料
| 型號： | EVAL-ADF4154EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4154EB1 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4154 |
| 主要屬性： | 單路分?jǐn)?shù)-N PLL |
| 次要屬性： | 19.2MHz PFD 圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4154BCPZ-ND - IC FRACTION-N FREQ SYNTH 20LFCSP ADF4154BRU-REEL7-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4154BCPZ-RL7-ND - IC FRACTION-N FREQ SYNTH 20LFCSP ADF4154BRUZ-RL7TR-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4154BRUZ-RL-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4154BRU-REEL-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4154BCPZ-RL-ND - IC FRACTION-N FREQ SYNTH 20LFCSP ADF4154BRUZ-ND - IC FRAC-N FREQ SYNTH 16-TSSOP ADF4154BRU-ND - IC FRAC-N FREQ SYNTH 16-TSSOP |
ADF4154
Data Sheet
Rev. C | Page 20 of 24
In low spur mode (dither enabled), the repeat length is
extended to 221 cycles, regardless of the value of MOD, which
makes the quantization error spectrum appear as broadband
noise. This can degrade the in-band phase noise at the PLL
output by as much as 10 dB. Therefore, for lowest noise, dither
off is a better choice, particularly when the final loop BW is low
enough to attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation are interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (as is the case
with fractional-N synthesizers), spur sidebands appear on the
VCO output spectrum at an offset frequency that corresponds
to the beat note or the difference in frequency between an
integer multiple of the reference and the VCO frequency.
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the
reference, where the difference frequency can be inside the loop
bandwidth, thus the name integer boundary spurs.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such
mechanism is feedthrough of low levels of on-chip reference
switching noise through the RFIN pin back to the VCO, resulting
in reference spur levels as high as –90 dBc. Care should be
taken in the PCB layout to ensure that the VCO is well
separated from the input reference to avoid a possible feed-
through path on the board.
SPUR CONSISTENCY
When jumping from Frequency A to Frequency B and then
back again using fractional-N synthesizers, the spur levels often
differ each time Frequency A is programmed. However, in the
ADF4154, the spur levels on any particular channel are always
consistent.
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help the user
implement the PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLL software. The software designs,
simulates, and analyzes the entire PLL frequency and time
domain response. Various passive and active filter architectures
are allowed.
INTERFACING
The ADF4154 has a simple, SPI-compatible serial interface for
writing to the device. SCLK, SDATA, and LE control the data
transfer. When LE (latch enable) is high, the 22 bits that have
been clocked into the input register on each rising edge of
SCLK are transferred to the appropriate latch. See Figure 2 for
the timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 s.
ADuC812 Interface
Figure 21 shows the interface between the ADF4154 and the
ADuC812 MicroConverter. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA set to 0. To initiate the operation, bring the
I/O port driving LE low. Each latch of the ADF4154 requires a
24-bit word, which is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. After the third byte is
written, the LE input should be brought high to complete the
transfer.
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that the
maximum rate at which the output frequency can be changed is
180 kHz.
ADuC812
ADF4154
SCLOCK
SCLK
SDATA
LE
MUXOUT
(LOCK DETECT)
MOSI
I/O PORTS
04833-
024
Figure 21. ADuC812-to-ADF4154 Interface
ADSP-21xx Interface
Figure 22 shows the interface between the ADF4154 and the
ADSP-21xx digital signal processor. As discussed previously, the
ADF4154 requires a 24-bit serial word for each latch write. The
easiest way to accomplish this using a device in the ADSP-21xx
family is to use the autobuffered transmit mode of operation
with alternate framing. This provides a means for transmitting
an entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store each of the three 8-bit bytes, enable the autobuffered
mode, and write to the transmit register of the DSP. This last
operation initiates the autobuffered transfer.
ADSP-21xx
ADF4154
SCLOCK
SCLK
SDATA
LE
MUXOUT
(LOCK DETECT)
DT
TFS
I/O FLAGS
04833-
025
Figure 22. ADSP-21xx-to-ADF4154 Interface
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADF4156EBZ1 | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| EVAL-ADF4157EB1Z | 功能描述:BOARD EVALUATION FOR ADF4157 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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