- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄18724 > EVAL-ADF4150HVEB1Z (Analog Devices Inc)EVAL BOARD FOR ADF4150HV PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADF4150HVEB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ADF4150HV |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N 合成器（RF） |
| 頻率： | 3GHz |
| 適用于相關(guān)產(chǎn)品： | ADF4150HV |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
ADF4150HV
Rev. 0 | Page 22 of 28
PHASE RESYNC
In the example shown in Figure 27, the PFD reference is 25 MHz
and MOD is 125 for a 200 kHz channel spacing. tSYNC is set to
400 μs by programming CLK_DIV_VALUE = 80.
The output of a fractional-N PLL can settle to any one of the
MOD phase offsets with respect to the input reference, where
MOD is the fractional modulus. The phase resync feature of
the ADF4150HV produces a consistent output phase offset with
respect to the input reference. This is necessary in applications
where the output phase and frequency are important, such as
digital beamforming. For information about how to program
a specific RF output phase when using phase resync, see the
Phase Programmability section.
LE
PHASE
FREQUENCY
SYNC
(INTERNAL)
–100
0
100 200
1000
300
400
500 600 700 800
900
TIME (s)
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
tSYNC
LAST CYCLE SLIP
PLL SETTLES TO
INCORRECT PHASE
09
05
8-
0
25
Phase resync is enabled by setting Bits[DB16:DB15] in
Register 3 to 10. When phase resync is enabled, an internal
timer generates sync signals at intervals of tSYNC given by the
following formula:
tSYNC = CLK_DIV_VALUE × MOD × tPFD
where:
CLK_DIV_VALUE is the decimal value programmed in
Bits[DB14:DB3] of Register 3 and can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bits[DB14:DB3]
of Register 1.
tPFD is the PFD reference period.
Figure 27. Phase Resync Example
Phase Programmability
The phase word in Register 1 controls the RF output phase. As
this word is swept from 0 to MOD, the RF output phase sweeps
over a 360° range in steps of 360°/MOD.
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The tSYNC time must be programmed to
a value that is at least as long as the worst-case lock time. This
guarantees that the phase resync occurs after the last cycle slip
in the PLL settling transient.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PROPOWER-2.5V-KIT | KIT IN-LINE REGULATOR +2.5V |
| TC32N6C32K7680 | OSCILLATOR 32.7680 KHZ 2.5V SMD |
| TC32L6C32K7680 | OSCILLATOR 32.7680 KHZ 3.3V SMD |
| 80-7 | NAIL HARNESS BOARD 1.75" |
| CB-OBS411I-04-B | KIT EVAL OBS411 USB |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADF4151EB1Z | 制造商:Analog Devices 功能描述:EVAL PLL FREQ SYNTH ADF4151 制造商:Analog Devices 功能描述:ADF4151, PLL SYNTHESIZER, EVAL BOARD; Silicon Manufacturer:Analog Devices; Kit Application Type:Clock & Timing; Application Sub Type:PLL Frequency Synthesizer; Kit Contents:Software CD, EVAL-ADF4151EB1Z Board; Features:Fractional-N ;RoHS Compliant: Yes |
| EVAL-ADF4153EB1 | 制造商:Analog Devices 功能描述:Evaluation Board For ADF4153 制造商:Analog Devices 功能描述:IC EVALUATION ((NS)) |
| EVAL-ADF4153EBZ1 | 功能描述:BOARD EVAL FOR ADF4153 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADF4154EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N Frequency Synthesizer |
| EVAL-ADF4154EBZ1 | 功能描述:BOARD EVALUATION FOR ADF4154EB1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。