TA
參數(shù)資料
型號(hào)： EVAL-ADAU1442EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 89/93頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1442
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1442
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 電路板，線纜，說明文檔，GPIO 子板，電源
ADAU1442/ADAU1445/ADAU1446
Data Sheet
Rev. D | Page 8 of 92
DIGITAL TIMING SPECIFICATIONS
TA = 40°C to +105°C, DVDD = 1.8 V, IOVDD = 3.3 V.
Table 4.
Parameter1
Min
Max
Unit
Description
MASTER CLOCK
fMP
2.822
24.576
MHz
Master clock (MCLK) frequency. See the Master Clock and PLL section.
tMP
40.69
354.36
ns
Master clock (MCLK) period. See the
tMD
25
75
%
Master clock (MCLK) duty cycle.
CLKOUT Jitter
250
ps
Cycle-to-cycle rms average.
CORE CLOCK
fCORE
172.032
MHz
DSP core clock frequency.
SERIAL PORT
fBCLK
24.576
MHz
BCLK frequency.
tBCLK
40.69
ns
BCLK period.
tBIL
30
ns
BCLKx low pulse width, slave mode.
tBIH
30
ns
BCLKx high pulse width, slave mode.
tLIS
20
ns
LRCLKx setup to BCLKx input rising edge, slave mode.
tLIH
20
ns
LRCLKx hold from BCLKx input rising edge, slave mode.
tSIS
10
ns
SDATA_INx setup to BCLKx input rising edge.
tSIH
10
ns
SDATA_INx hold from BCLKx input rising edge.
tTS
5
ns
BCLKx output falling edge to LRCLKx output timing skew.
tSODS
30
ns
SDATA_OUTx delay in slave mode from BCLKx output falling edge.
tSODM
30
ns
SDATA_OUTx delay in master mode from BCLKx output falling edge.
SPI PORT
fCCLK write
32
MHz
CCLK frequency.2
fCCLK read
16
MHz
CCLK frequency.2
tCCPL
20
ns
CCLK pulse width low.
tCCPH
20
ns
CCLK pulse width high.
tCLS
0
ns
CLATCH setup to CCLK rising edge.
tCLH
35
ns
CLATCH hold from CCLK rising edge.
tCLPH
20
ns
CLATCH pulse width high.
tCLDLY
20
ns
Minimum delay between CLATCH low pulses.
tCDS
0
ns
CDATA setup to CCLK rising edge.
tCDH
35
ns
CDATA hold from CCLK rising edge.
tCOV
40
ns
COUT valid output delay from CCLK falling edge.
I2C PORT
fSCL
400
kHz
SCL clock frequency.
tSCLH
0.6
s
SCL pulse width high.
tSCLL
1.3
s
SCL pulse width low.
tSCS
0.6
s
Start and repeated start condition setup time.
tSCH
0.6
s
Start condition hold time.
tDS
100
ns
Data setup time.
tDH
0.9
s
Data hold time.
tSCLR
300
ns
SCL rise time.
tSCLF
300
ns
SCL fall time.
tSDR
300
ns
SDA rise time.
tSDF
300
ns
SDA fall time.
tBFT
1.3
s
Bus-free time between stop and start.
MULTIPURPOSE PINS AND RESET
fMP
fS/2
Hz
MPx maximum switching rate.
tMPIL
1.5 × 1/fS,NORMAL
s
MPx pin input latency until high/low value is read by core. Guaranteed
by design.
tRLPW
10
ns
RESET low pulse width.
1
All timing specifications are given for the default (I2S) states of the serial audio input ports and the serial audio output ports (see Table 26 and Table 30).
2
Maximum SPI CCLK clock frequency is dependent on current drive strength and capacitive loads on the circuit board.
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