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參數(shù)資料
型號(hào)： EVAL-AD7762EDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/29頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL CONTROL AD7762
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： ±3.25 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 958mW @ 625kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7762
已供物品： 板，CD
AD7762
Data Sheet
Rev. A | Page 8 of 28
Pin No.
Mnemonic
Description
10
VREF+
Reference Input. The input range of this pin is determined by the reference buffer supply voltage
(AVDD4). See the Reference Voltage Filtering section for more details.
8
DECAPA
Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1.
30
DECAPB
Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
17
RBIAS
Bias Current Setting Pin. A resistor must be inserted between this pin and AGND1. For more details, see
45 to 52,
54 to 61
DB15 to DB8
DB7 to DB0
16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR
pin. The operating voltage for these pins is determined by the VDRIVE voltage. See the AD7762 Interface
section for more details.
37
RESET
A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin
low keeps the AD7762 in a reset state.
3
MCLK
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends
on the frequency of this clock. See the section Clocking the AD7762 for more details.
2
MCLKGND
Master Clock Ground Sensing Pin.
36
SYNC
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to
synchronize multiple devices in a system.
39
RD/WR
Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and
from the AD7762. If this pin is low when CS is low, a read takes place. If this pin is high and CS is low, a
write occurs. See the AD7762 Interface section for more details.
38
DRDY
Data Ready Output. Each time that new conversion data is available, an active low pulse, ICLK period
wide, is produced on this pin. See the AD7762 Interface section for more details.
40
CS
Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from the
AD7762. See the AD7762 Interface section for more details.
EPAD
Exposed pad. Connect the exposed pad to AGNDx with six to eight vias.
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