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參數(shù)資料
| 型號： | EVAL-AD7762EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/29頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL CONTROL AD7762 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 625k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±3.25 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 958mW @ 625kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7762 |
| 已供物品： | 板，CD |
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AD7762
Data Sheet
Rev. A | Page 24 of 28
STATUS REGISTER (READ ONLY)
MSB
LSB
PART 1
PART 0
DIE 2
DIE 1
DIE 0
DVALID
LPWR
OVR
DL OK
Filter OK
U Filter
BYP F3
1
DEC2
DEC1
DEC0
Table 17.
Bit
Mnemonic
Comment
15, 14
PART1:0
Part Number. These bits are constant for the AD7762.
13 to 11
DIE2:0
Die Number. These bits reflect the current AD7762 die number for identification purposes within a system.
10
DVALID
Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation.
9
LPWR
Low Power. If the AD7762 is operating in low power mode, this bit is set to 1.
8
OVR
If the current analog input exceeds the current overrange threshold, this bit is set.
7
DL OK
When downloading a user filter to the AD7762, a checksum is generated. This checksum is compared to the one
downloaded following the coefficients. If these checksums agree, this bit is set.
6
Filter OK
When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This
generated checksum is compared to the one downloaded. If they match, this bit is set.
5
U Filter
If a user-defined filter is in use, this bit is set.
4
BYP F3
Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.
3
1
This bit is always set.
2-0
DEC2:0
Decimation Rate. These correspond to the bits set in Control Register 1.
OFFSET REGISTER—ADDRESS 0X0003
Non-bitmapped, Default Value 0x0000
The offset register uses twos complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum
negative value) correspond to an offset of +0.78125% and 0.78125%, respectively. Offset correction is applied after any gain correction.
Using the default gain value of 1.25 and assuming a reference voltage of 4.096 V, the offset correction range is approximately ±25 mV.
GAIN REGISTER—ADDRESS 0X0004
Non-bitmapped, Default Value 0xA000
The gain register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a
full-scale digital output when the input is at 80% of VREF. This ties in with the maximum analog input range of ±80% of VREF p-p.
OVERRANGE REGISTER—ADDRESS 0X0005
Non-bitmapped, Default Value 0xCCCC
The overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum
propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of VREF
(the maximum permitted analog input voltage). Assuming VREF = 4.096 V, the bit is then set when the input voltage exceeds approximately
6.55 V p-p differential. Note that the overrange bit is also set immediately if the analog input voltage exceeds 100% of VREF for more than
four consecutive samples at the modulator rate.
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