Table 2. (AVDD = 5 V ± 5" />
參數(shù)資料
型號(hào)： EVAL-AD7734EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7734
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： 串行
輸入范圍： ±10 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 85mW @ 5V
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7734
已供物品： 板，纜線，CD
產(chǎn)品目錄頁(yè)面： 779 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD7734BRUZ-REEL7TR-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP
AD7734BRUZ-REEL-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP
AD7734BRUZ-ND - IC ADC 24BIT 4-CH 28-TSSOP
AD7734BRU-ND - IC ADC 24BIT 4-CH 28-TSSOP
AD7734
Data Sheet
Rev. A | Page 6 of 32
TIMING SPECIFICATIONS
Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.)1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Master Clock Range
1
6.144
MHz
t
1
50
ns
SYNC Pulsewidth
t
2
500
ns
RESET Pulsewidth
Read Operation
t
4
0
ns
CS Falling Edge to SCLK Falling Edge Setup Time
t
5
SCLK Falling Edge to Data Valid Delay
0
60
ns
DV
DD of 4.75 V to 5.25 V
0
80
ns
DV
DD of 2.7 V to 3.3 V
t
CS Falling Edge to Data Valid Delay
0
60
ns
DV
DD of 4.75 V to 5.25 V
0
80
ns
DV
DD of 2.7 V to 3.3 V
t
6
50
ns
SCLK High Pulsewidth
t
7
50
ns
SCLK Low Pulsewidth
t
8
0
ns
CS Rising Edge after SCLK Rising Edge Hold Time
t
9
10
80
ns
Bus Relinquish Time after SCLK Rising Edge
Write Operation
t
11
0
ns
CS Falling Edge to SCLK Falling Edge Setup
t
12
30
ns
Data Valid to SCLK Rising Edge Setup Time
t
13
25
ns
Data Valid after SCLK Rising Edge Hold Time
t
14
50
ns
SCLK High Pulsewidth
t
15
50
ns
SCLK Low Pulsewidth
t
16
0
ns
CS Rising Edge after SCLK Rising Edge Hold Time
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD) and timed from a voltage level of
2 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the V
OL or VOH limits.
3 This specification is relevant only if CS goes low while SCLK is low.
4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
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