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參數(shù)資料
| 型號(hào)： | EVAL-AD7734EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7734 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15.4k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 85mW @ 5V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7734 |
| 已供物品： | 板，纜線，CD |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD7734BRUZ-REEL7TR-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP AD7734BRUZ-REEL-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP AD7734BRUZ-ND - IC ADC 24BIT 4-CH 28-TSSOP AD7734BRU-ND - IC ADC 24BIT 4-CH 28-TSSOP |
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Data Sheet
AD7734
Rev. A | Page 15 of 32
REGISTER ACCESS
The AD7734 is configurable through a series of registers. Some
of them configure and control general AD7734 features, while
others are specific to each channel. The register data widths
vary from 8 bits to 24 bits. All registers are accessed through the
communications register, i.e., any communication to the
AD7734 must start with a write to the communications register
specifying which register will be subsequently read or written.
COMMUNICATIONS REGISTER
8 Bits, Write-Only Register, Address 00h
All communications to the part must start with a write
operation to the communications register. The data written to
the communications register determines whether the
subsequent operation will be a read or write and to which
register this operation will be directed. The digital interface
defaults to expect write operation to the communications
register after power-on, after reset, or after the subsequent read
or write operation to the selected register is complete. If the
interface sequence is lost, the part can be reset by writing at
least 32 serial clock cycles with DIN high and CS low. (Note that
all of the parts, including the modulator, filter, interface, and all
registers are reset in this case.) Remember to keep DIN low
while reading 32 bits or more either in continuous read mode or
with the DUMP bit and “24/16” bit in the mode register set.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
0
R/W
6-Bit Register Address
Bit
Mnemonic
Description
7
0
This bit must be 0 for proper operation.
6
R/W
A 0 in this bit indicates that the next operation will be a write to a specified register. A 1 in this bit indicates
that the next operation will be a read from a specified register.
5–0
Address
Address specifying to which register the read or write operation will be directed. For channel specific registers,
two LSBs, i.e., Bit 1 and Bit 0, specify the channel number. When the subsequent operation writes to the Mode
register, two LSBs specify the channel selected for operation determined by the mode register value (see Table
Table 14.
Bit 2
Bit 1
Bit 0
Channel
Input
0
AIN0
0
1
AIN1
0
1
0
2
AIN2
0
1
3
AIN3
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