參數(shù)資料
型號(hào)： EVAL-AD7730LEBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 50/53頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7730
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 600
數(shù)據(jù)接口： 串行
輸入范圍： ±80 mV
在以下條件下的電源（標(biāo)準(zhǔn)）： 125mW @ 600SPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7730
已供物品： 板，CD
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AD7730/AD7730L
–6–
Figure 2. Detailed Functional Block Diagram
SIGMA-
DELTA
MODULATOR
AD7730
6-BIT
DAC
SERIAL INTERFACE
AND CONTROL LOGIC
REGISTER BANK
CLOCK
GENERATION
PROGRAMMABLE
DIGITAL
FILTER
SIGMA-DELTA A/D CONVERTER
BUFFER
PGA
AGND
AVDD
VBIAS
AIN1(+)
AIN1(–)
AIN2(+)/D1
AIN2(–)/D0
ACX
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
CS
DIN
DOUT
RESET
RDY
POL
DGND
AGND
AVDD
DVDD
REF IN(–) REF IN(+)
MUX
REFERENCE DETECT
AC
EXCITATION
CLOCK
CALIBRATION
MICROCONTROLLER
+
REGISTER BANK
THIRTEEN REGISTERS CONTROL
ALL FUNCTIONS ON THE PART AND
PROVIDE STATUS INFORMATION
AND CONVERSION RESULTS
SEE PAGE 11
STANDBY MODE
THE STANDBY MODE REDUCES
POWER CONSUMPTION TO 5 A
SEE PAGE 33
CLOCK OSCILLATOR
CIRCUIT
THE CLOCK SOURCE FOR THE
PART CAN BE PROVIDED BY AN
EXTERNALLY-APPLIED CLOCK OR
BY CONNECTING A CRYSTAL OR
CERAMIC RESONATOR ACROSS
THE CLOCK PINS
SEE PAGE 32
SERIAL INTERFACE
SPI*-COMPATIBLE OR DSP-
COMPATIBLE SERIAL INTERFACE
WHICH CAN BE OPERATED FROM
JUST THREE WIRES. ALL
FUNCTIONS ON THE PART
CAN BE ACCESSED VIA
THE SERIAL INTERFACE
SEE PAGE 35
OFFSET/TARE DAC
ALLOWS A PROGRAMMED
VOLTAGE TO BE EITHER ADDED
OR SUBTRACTED FROM THE
ANALOG INPUT SIGNAL BEFORE
IT IS APPLIED TO THE PGA
SEE PAGE 24
OUTPUT DRIVERS
THE SECOND ANALOG INPUT
CHANNEL CAN BE
RECONFIGURED TO BECOME TWO
OUTPUT DIGITAL PORT LINES
WHICH CAN BE PROGRAMMED
OVER THE SERIAL INTERFACE
SEE PAGE 33
AC EXCITATION
FOR AC-EXCITED BRIDGE
APPLICATIONS, THE ACX
OUTPUTS PROVIDE SIGNALS
THAT CAN BE USED TO SWITCH
THE POLARITY OF THE BRIDGE
EXCITATION VOLTAGE
SEE PAGE 41
ANALOG MULTIPLEXER
A TWO-CHANNEL DIFFERENTIAL
MULTIPLEXER SWITCHES ONE OF
THE TWO DIFFERENTIAL INPUT
CHANNELS TO THE BUFFER
AMPLIFIER. THE MULTIPLEXER IS
CONTROLLED VIA THE SERIAL
INTERFACE
SEE PAGE 24
SIGMA DELTA ADC
THE SIGMA DELTA
ARCHITECTURE ENSURES 24 BITS
NO MISSING CODES. THE
ENTIRE SIGMA DELTA. ADC CAN
BE CHOPPED TO REMOVE DRIFT
ERRORS
SEE PAGE
DIFFERENTIAL
REFERENCE
THE REFERENCE INPUT TO THE
PART IS DIFFERENTIAL AND
FACILITATES RATIOMETRIC
OPERATION. THE REFERENCE
VOLTAGE CAN BE SELECTED TO
BE NOMINALLY +2.5V OR +5V
SEE PAGE 25
PROGRAMMABLE
DIGITAL FILTER
TWO STAGE FILTER THAT
ALLOWS PROGRAMMING OF
OUTPUT UPDATE RATE AND
SETTLING TIME AND WHICH HAS
A FAST STEP MODE
(SEE FIGURE 3)
SEE PAGE 26
SIGMA-DELTA ADC
THE SIGMA-DELTA
ARCHITECTURE ENSURES 24 BITS
NO MISSING CODES. THE
ENTIRE SIGMA-DELTA ADC CAN
BE CHOPPED TO REMOVE DRIFT
ERRORS
SEE PAGE 26
PROGRAMMABLE GAIN
AMPLIFIER
THE PROGRAMMABLE GAIN
AMPLIFIER ALLOWS FOUR
UNIPOLAR AND FOUR BIPOLAR
INPUT RANGES FROM
+10mV TO +80mV
SEE PAGE 24
BUFFER AMPLIFIER
THE BUFFER AMPLIFIER
PRESENTS A HIGH IMPEDANCE
INPUT STAGE FOR THE ANALOG
INPUTS ALLOWING SIGNIFICANT
EXTERNAL SOURCE
IMPEDANCES
SEE PAGE 24
BURNOUT CURRENTS
TWO 100nA BURNOUT
CURRENTS ALLOW THE USER
TO EASILY DETECT IF A
TRANSDUCER HAS BURNT
OUT OR GONE OPEN-CIRCUIT
SEE PAGE 25
+/–
*SPI IS A TRADEMARK OF MOTOROLA, INC.
REV. B
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