參數(shù)資料
型號(hào)： EVAL-AD7691CBZ
廠商： Analog Devices Inc
文件頁數(shù)： 13/28頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7691CBZ
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
ADC 的數(shù)量： 1
位數(shù)： 18
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行
輸入范圍： ±VREF
在以下條件下的電源（標(biāo)準(zhǔn)）： 10.6mW @ 250kSPS，5 V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7691
已供物品： 板
相關(guān)產(chǎn)品： AD7691BCPZRL7TR-ND - IC ADC 18BIT SAR 250KSPS 10LFCSP
AD7691BCPZRL-ND - IC ADC 18BIT SAR 250KSPS 10LFCSP
AD7691BRMZ-RL7-ND - IC ADC 18BIT SAR 250KSPS 10-MSOP
AD7691BRMZ-ND - IC ADC 18BIT SAR 250KSPS 10-MSOP
AD7691
Data Sheet
Rev. C | Page 20 of 28
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7691s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7691s is shown in
Figure 39, and the corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7691 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 18th SCK
falling edge, or when SDI goes high, whichever occurs first, SDO
returns to high impedance and another AD7691 can be read.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
CNV
SCK
SDO
SDI
CNV
SCK
SDO
SDI
AD7691
06
14
6-
0
1
5
Figure 39. 4-Wire CS Mode Without Busy Indicator Connection Diagram
SDO
D17
D16
D15
D1
D0
tDIS
SCK
12
3
34
35
36
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI (CS1)
CNV
tSSDICNV
tHSDICNV
D1
16
17
tSCK
tSCKL
tSCKH
D0
D17
D16
19
20
18
SDI (CS2)
06
14
6-
0
16
Figure 40. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing
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