參數(shù)資料
型號(hào)： EVAL-AD7691CBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/28頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD7691CBZ
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
ADC 的數(shù)量： 1
位數(shù)： 18
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行
輸入范圍： ±VREF
在以下條件下的電源（標(biāo)準(zhǔn)）： 10.6mW @ 250kSPS，5 V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7691
已供物品： 板
相關(guān)產(chǎn)品： AD7691BCPZRL7TR-ND - IC ADC 18BIT SAR 250KSPS 10LFCSP
AD7691BCPZRL-ND - IC ADC 18BIT SAR 250KSPS 10LFCSP
AD7691BRMZ-RL7-ND - IC ADC 18BIT SAR 250KSPS 10-MSOP
AD7691BRMZ-ND - IC ADC 18BIT SAR 250KSPS 10-MSOP
AD7691
Data Sheet
Rev. C | Page 18 of 28
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 35, and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers, but CNV must be returned high before
the minimum conversion time elapses and then held high for
the maximum possible conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete,
the AD7691 enters the acquisition phase and powers down.
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge can allow a faster reading rate, provided it has
an acceptable hold time. After the 18th SCK falling edge, or
when CNV goes high, whichever occurs first, SDO returns to
high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7691
06
14
6-
0
11
Figure 35. 3-Wire CS Mode Without Busy Indicator
Connection Diagram (SDI High)
SDO
D17
D16
D15
D1
D0
tDIS
SCK
123
16
17
18
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
06
14
6-
0
12
Figure 36. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
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