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參數(shù)資料
| 型號(hào)： | EVAL-AD7623CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7623 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1.33M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 50mW @ 1.33MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7623 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7623ASTZ-ND - IC ADC 16BIT 1.33MSPS DFF 48LQFP AD7623ACPZ-ND - IC ADC 16BIT 1.33MSPS 48LFCSP AD7623ACPZRL-ND - IC ADC 16BIT 1.33MSPS 48LFCSP AD7623ASTZRL-ND - IC ADC 16BIT 1.33MSPS DFF 48LQFP |
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AD7623
Rev. 0 | Page 22 of 28
05574-035
PREVIOUS
CONVERSION
t13
t12
t3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t4
t1
Figure 35. Slave Parallel Data Timing for Reading (Read During Convert)
8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 36, when BYTESWAP is low, the LSB byte is
output on D[7:0] and the MSB is output on D[15:8]. When
BYTESWAP is high, the LSB and MSB bytes are swapped, and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0]. This
interface can be used in both master and slave parallel reading
modes.
05574-036
CS
RD
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HIGH BYTE
LOW BYTE
HIGH BYTE
HI-Z
t12
t13
Figure 36. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7623 is configured to use the serial interface when
SER/PAR is held high. The AD7623 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7623 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7623 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted, if desired. Depending on the read
during convert input, RDC/SDIN, the data can be read after
each conversion or during the following conversion. Figure 37
and Figure 38 show detailed timing diagrams of these two
modes.
Usually, because the AD7623 is used with a fast throughput, the
master read during conversion mode is the most recommended
serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions. In this mode,
the SCLK period changes since the LSBs require more time to
settle and the SCLK is derived from the SAR conversion cycle.
In read after conversion mode, unlike other modes, the BUSY
signal returns low after the 16 data bits are pulsed out and not at
the end of the conversion phase, resulting in a longer BUSY
width. As a result, the maximum throughput cannot be
achieved in this mode.
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| EVAL-AD7623EDZ | 功能描述:BOARD EVAL FOR AD7623 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7625EDZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board 16-BIT 5MSPS ADC I.C RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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| EVAL-AD7631CBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) |
| EVAL-AD7631EDZ | 功能描述:BOARD EVAL FOR AD7631 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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