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參數(shù)資料
| 型號： | EVAL-AD7190EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7190 |
| 設計資源： | EVAL-AD7190EBZ Schematic |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF/增益 |
| 在以下條件下的電源（標準）： | 36.8mW @ 4.8kSPS |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7190 |
| 已供物品： | 板，CD |
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Data Sheet
AD7190
Rev. C | Page 35 of 40
SYSTEM SYNCHRONIZATION
The SYNC input allows the user to reset the modulator and the
digital filter without affecting any of the setup conditions on the
part. This allows the user to start gathering samples of the analog
input from a known point in time, that is, the rising edge of
SYNC. SYNC needs to be taken low for four master clock cycles
to implement the synchronization function.
If multiple AD7190 devices are operated from a common master
clock, they can be synchronized so that their data registers are
updated simultaneously. A falling edge on the SYNC pin resets
the digital filter and the analog modulator and places the AD7190
into a consistent, known state. While the SYNC pin is low, the
AD7190 is maintained in this state. On the SYNC rising edge,
the modulator and filter are taken out of this reset state and, on
the next clock edge, the part starts to gather input samples again.
In a system using multiple AD7190 devices, a common signal to
their SYNC pins synchronizes their operation. This is normally
done after each AD7190 has performed its own calibration or
has had calibration coefficients loaded into its calibration
registers. The conversions from the AD7190s are then
synchronized.
The part is taken out of reset on the master clock falling edge
following the SYNC low-to-high transition. Therefore, when
multiple devices are being synchronized, the SYNC pin should
be taken high on the master clock rising edge to ensure that all
devices begin sampling on the master clock falling edge. If the
SYNC pin is not taken high in sufficient time, it is possible to
have a difference of one master clock cycle between the devices;
that is, the instant at which conversions are available differs
from part to part by a maximum of one master clock cycle.
The SYNC pin can also be used as a start conversion command.
In this mode, the rising edge of SYNC starts conversion, and the
falling edge of RDY indicates when the conversion is complete.
The disadvantage of this scheme is that the settling time of the
filter has to be allowed for each data register update. This means
that the rate at which the data register is updated is reduced. For
example, if the ADC is configured to use the sinc4 filter, zero
latency is disabled and chop is disabled, the data register update
takes four times longer.
TEMPERATURE SENSOR
Embedded in the AD7190 is a temperature sensor. This is
selected using the CH2 bit in the configuration register. When
the CH2 bit is set to 1, the temperature sensor is enabled. When
the temperature sensor is selected and bipolar mode is selected,
the device should return a code of 0x800000 when the temper-
ature is 0 K. A one-point calibration is needed to get the optimum
performance from the sensor. Therefore, a conversion at 25°C
should be recorded and the sensitivity calculated. The sensitivity
is approximately 2815 codes/°C. The equation for the temperature
sensor is
Temp (K) = (Conversion – 0x800000)/2815 K
Temp (°C) = Temp (K) – 273
Following the one point calibration, the internal temperature
sensor has an accuracy of ±2 °C, typically.
BRIDGE POWER-DOWN SWITCH
In bridge applications such as strain gauges and load cells, the
bridge itself consumes the majority of the current in the system.
For example, a 350 Ω load cell requires 15 mA of current when
excited with a 5 V supply. To minimize the current consumption
of the system, the bridge can be disconnected (when it is not
being used) using the bridge power-down switch. Figure 18
shows how the bridge power-down switch is used. The switch
can withstand 30 mA of continuous current, and it has an on
resistance of 10 Ω maximum.
LOGIC OUTPUTS
The AD7190 has four general-purpose digital outputs, P0, P1,
P2, and P3. These are enabled using the GP32EN and GP10EN
bits in the GPOCON register. The pins can be pulled high or
low using the P0DAT to P3DAT bits in the GPOCON register;
that is, the value at the pin is determined by the setting of the
P0DAT to P3DAT bits. The logic levels for these pins are
determined by AVDD rather than by DVDD. When the GPOCON
register is read, the P0DAT to P3DAT bits reflect the actual
value at the pins. This is useful for short-circuit detection.
These pins can be used to drive external circuitry, for example,
an external multiplexer. If an external multiplexer is used to
increase the channel count, the multiplexer logic pins can be
controlled via the AD7190 general-purpose output pins. The
general-purpose output pins can be used to select the active
multiplexer pin. Because the operation of the multiplexer is
independent of the AD7190, the AD7190 modulator and filter
should be reset using the SYNC pin each time that the multi-
plexer channel is changed.
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