參數(shù)資料
型號(hào)： EVAL-AD7190EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/41頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7190
設(shè)計(jì)資源： EVAL-AD7190EBZ Schematic
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 4.8k
數(shù)據(jù)接口： 串行
輸入范圍： ±VREF/增益
在以下條件下的電源（標(biāo)準(zhǔn)）： 36.8mW @ 4.8kSPS
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7190
已供物品： 板，CD
AD7190
Data Sheet
Rev. C | Page 28 of 40
50 Hz/60 Hz Rejection
Normal mode rejection is one of the main functions of the
digital filter. With chop disabled, 50 Hz rejection is obtained
when the output data rate is set to 50 Hz, whereas 60 Hz
rejection is achieved when the output data rate is set to 60 Hz.
Simultaneous 50 Hz/60 Hz rejection is obtained when the
output data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz
rejection can also be achieved using the REJ60 bit in the mode
register. When the output data rate is programmed to 50 Hz and
the REJ60 bit is set to 1, notches are placed at both 50 Hz and
60 Hz.
Figure 23 and Figure 24 show the frequency response of the
sinc4 and sinc3 filters, respectively, when the output data rate is
programmed to 50 Hz and REJ60 is set to 1.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
25
50
75
100
125
150
FILTE
R
GA
IN
(
dB
)
FREQUENCY (Hz)
07640-
017
Figure 23. Sinc4 Filter Response (50 Hz Output Data Rate, REJ60 = 1)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
25
50
75
100
125
150
FILTE
R
GA
IN
(
dB
)
FREQUENCY (Hz)
07640-
018
Figure 24. Sinc3 Filter Response (50 Hz Output Data Rate, REJ60 = 1)
Again, the sinc4 filter provides better 50 Hz/60 Hz rejection
than the sinc3 filter. In addition, better stop-band attenuation is
achieved with the sinc4 filter.
When chop is enabled, lower output data rates must be used to
achieve 50 Hz and 60 Hz rejection. With REJ60 set to 1, an output
data rate of 12.5 Hz gives simultaneous 50 Hz/60 Hz rejection
when the sinc4 filter is selected, whereas an output data rate of
16.7 Hz gives simultaneous 50 Hz/ 60 Hz rejection when the sinc3
filter is used. Figure 25 and Figure 26 show the filter response for
both output data rates when REJ60 is set to 1.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
25
50
75
100
125
150
FILTE
R
GA
IN
(
dB
)
FREQUENCY (Hz)
07640-
125
Figure 25. Sinc4 Filter Response (12.5 Hz Output Data Rate,
Chop Enabled, REJ60 = 1)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
25
50
75
100
125
150
FILTE
R
GA
IN
(
dB
)
FREQUENCY (Hz)
07640-
126
Figure 26. Sinc3 Filter Response (16.7 Hz Output Data Rate,
Chop Enabled, REJ60 = 1)
Zero Latency
Zero latency is enabled by setting the SINGLE bit in the mode
register to 1. With zero latency, the complete settling time is
allowed for each conversion. Therefore,
fADC = 1/tSETTLE
Zero latency means that the output data rate is constant
irrespective of the number of analog input channels enabled;
the user does not need to consider the effects of channel
changes on the output data rate. The disadvantages of zero
latency are the increased noise for a given output data rate
compared with the nonzero latency mode. For example, when
zero latency is not enabled, the AD7190 has a noise-free
resolution of 18.5 bits when the output data rate is 50 Hz and
the gain is set to 128. When zero latency is enabled, the ADC
has a resolution of 17.5 bits peak-to-peak when the output data
rate is 50 Hz. The filter response also changes. Figure 19 shows
the filter response for the sinc4 filter when the output data rate
is 50 Hz (zero latency disabled). Figure 27 shows the filter
response when zero latency is enabled and the output data rate
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