參數(shù)資料
型號(hào): EVAL-AD7190EBZ
廠商: Analog Devices Inc
文件頁數(shù): 21/41頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD7190
設(shè)計(jì)資源: EVAL-AD7190EBZ Schematic
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 24
采樣率(每秒): 4.8k
數(shù)據(jù)接口: 串行
輸入范圍: ±VREF/增益
在以下條件下的電源(標(biāo)準(zhǔn)): 36.8mW @ 4.8kSPS
工作溫度: -40°C ~ 105°C
已用 IC / 零件: AD7190
已供物品: 板,CD
Data Sheet
AD7190
Rev. C | Page 27 of 40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
25
50
75
100
125
150
FILTE
R
GA
IN
(
dB
)
FREQUENCY (Hz)
07640-
014
Figure 20. Sinc3 Filter Response (50 Hz Output Data Rate)
The sinc4 filter provides 50 Hz (±1 Hz) rejection in excess of
120 dB, assuming a stable master clock, while the sinc3 filter
gives a rejection of 100 dB. The stop-band attenuation is
typically 53 dB for the sinc4 filter but equal to 40 dB for the
sinc3 filter.
The 3 dB frequency for the sinc4 filter is equal to
f3dB = 0.23 × fADC
and for the sinc3 filter is equal to
f3dB = 0.272 × fADC
Chop Enabled
With chop enabled, the ADC offset and offset drift are
minimized. When chop is enabled, the analog input pins are
continuously swapped. Therefore, with the analog input pins
connected in one direction, the settling time of the sinc filter is
allowed to elapse until a valid conversion is available. The analog
input pins are then inverted and another valid conversion is
obtained. Subsequent conversions are then averaged so that the
offset is minimized. This continuous swapping of the analog
input pins and the averaging of subsequent conversions means
that the offset drift is also minimized.
Chopping affects the output data rate and settling time of the
ADC. For the sinc4 filter, the output data rate is equal to
fADC = fCLK/(4 × 1024 × FS[9:0])
For sinc3 filter, the output data rate is equal to
fADC = fCLK/(3 × 1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK = master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The value of FS[9:0] can be varied from 1 to 1023. This results
in an output data rate of 1.173 Hz to 1200 Hz for the sinc4 filter
and 1.56 Hz to 1600 Hz for the sinc3 filter. The settling time for
the sinc3 or sinc4 filter is equal to
tSETTLE = 2/fADC
Therefore, with chop enabled, the settling time is reduced for a
given output data rate compared to the chop disabled mode.
However, for a given FS[9:0] value, the output data rate is less
with chop enabled compared with the chop disabled mode.
For either the sinc3 or the sinc4 filter, the cutoff frequency f3dB is
equal to
f3dB = 0.24 × fADC
Figure 21 and Figure 22 show the filter response for the sinc4
and sinc3 filters, respectively, when chop is enabled. As shown
in the plots, the stop-band attenuation is less compared with the
chop disabled modes.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
25
50
75
100
125
150
FILTE
R
GA
IN
(
dB
)
FREQUENCY (Hz)
07640-
015
Figure 21. Sinc4 Filter Response (Output Data Rate = 12.5 Hz, Chop Enabled)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
25
50
75
100
125
150
FILTE
R
GA
IN
(
dB
)
FREQUENCY (Hz)
07640-
016
Figure 22. Sinc3 Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled)
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