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參數(shù)資料
| 型號： | EVAL-AD5780SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD5780 |
| 設計資源： | CN-0200 Circuit |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 18 |
| 數(shù)據接口： | DSP，MICROWIRE?，QSPI?，和 SPI? |
| 設置時間： | 2.5µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板，纜線，CD |
| 已用 IC / 零件： | AD5780 |
| 相關產品： | AD5780ACPZ-ND - IC DAC VOLT OUT 18BIT 24LFCSP |
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AD5780
Data Sheet
Rev. E | Page 18 of 28
THEORY OF OPERATION
The AD5780 is a high accuracy, fast settling, single, 18-bit,
serial input, voltage output DAC. It operates from a VDD supply
voltage of 7.5 V to 16.5 V and a VSS supply of 16.5 V to 2.5 V.
Data is written to the AD5780 in a 24-bit word format via a 3-wire
serial interface. The AD5780 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
VOUT pin clamped to AGND through a ~6 k internal resistor.
DAC ARCHITECTURE
The architecture of the AD5780 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 49.
The six MSBs of the 18-bit data-word are decoded to drive
63 switches, E0 to E62. Each of these switches connects one
of 63 matched resistors to either the buffered VREFP or buffered
VREFN voltage. The remaining 12 bits of the data-word drive the
S0 to S11 switches of a 12-bit voltage mode R-2R ladder network.
2R
S0
2R
S1
2R
S11
2R
E62
2R
E61
2R
E0
12-BIT R-2R LADDER
...
R
2R
VOUT
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
VREFP
VREFN
09649-
049
Figure 49. DAC Ladder Structure Serial Interface
SERIAL INTERFACE
The AD5780 has a 3-wire serial interface (SYNC, SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
input register consists of a R/W bit, three address bits, and
20 data bits as shown in Table 6. The timing diagram for this
operation is shown in Figure 2.
Table 6. Input Shift Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19 to DB0
R/W
Register address
Register data
Table 7. Decoding the Input Shift Register
R/W
Register Address
Description
0
No operation (NOP). Used in readback operations.
0
1
Write to the DAC register.
0
1
0
Write to the control register.
0
1
Write to the clearcode register.
0
1
0
Write to the software control register.
1
0
1
Read from the DAC register.
1
0
1
0
Read from the control register.
1
0
1
Read from the clearcode register.
1
X is don’t care.
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