參數(shù)資料
型號: EVAL-AD5621EBZ
廠商: Analog Devices Inc
文件頁數(shù): 9/24頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD5621
產(chǎn)品培訓模塊: DAC Architectures
標準包裝: 1
系列: nanoDAC™
DAC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 1.7M
數(shù)據(jù)接口: 串行
設(shè)置時間: 6µs
DAC 型: 電壓
工作溫度: -40°C ~ 125°C
已供物品:
已用 IC / 零件: AD5621
Data Sheet
AD5601/AD5611/AD5621
Rev. G | Page 17 of 24
AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x
Interface
Figure 48 shows a serial interface between the AD5601/AD5611/
AD5621 and the Blackfin ADSP-BF53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5601/AD5611/AD5621, the setup for the interface is as
follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/
AD5621, while TSCLK0 drives the SCLK of the part. The SYNC
is driven from TFS0.
Figure 48. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface
AD5601/AD5611/AD5621 to 80C51/80L51 Interface
Figure 49 shows a serial interface between the AD5601/
AD5611/AD5621 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TxD of the 80C51/80L51
drives SCLK of the AD5601/AD5611/AD5621, while RxD
drives the serial data line of the part. The SYNC signal is again
derived from a bit programmable pin on the port. In this case,
Port Line P3.3 is used. When data is to be transmitted to the
AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51
transmit data only in 8-bit bytes; therefore, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this
cycle. The 80C51/80L51 output the serial data LSB first. The
AD5601/AD5611/AD5621 require data with the MSB as the
first bit received. The 80C51/80L51 transmit routine should
take this into account.
Figure 49. AD5601/AD5611/AD5621 to 80C51/80L51 Interface
AD5601/AD5611/AD5621 to MICROWIRE Interface
Figure 50 shows an interface between the AD5601/AD5611/
AD5621 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock and is
clocked into the AD5601/AD5611/AD5621 on the rising edge
of the SK.
Figure 50. AD5601/AD5611/AD5621 to MICROWIRE Interface
ADSP-BF53x*
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
SDIN
SCLK
SYNC
06853-
047
80C51/80L51*
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
SDIN
06853-
048
MICROWIRE*
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
SDIN
06853-
049
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