參數(shù)資料
型號(hào): EVAL-AD5621EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/24頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD5621
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
系列: nanoDAC™
DAC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 1.7M
數(shù)據(jù)接口: 串行
設(shè)置時(shí)間: 6µs
DAC 型: 電壓
工作溫度: -40°C ~ 125°C
已供物品:
已用 IC / 零件: AD5621
AD5601/AD5611/AD5621
Data Sheet
Rev. G | Page 4 of 24
A Grade
B Grade
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.7
5.5
2.7
5.5
V
All digital inputs at 0 V or VDD
IDD for Normal Mode
DAC active and excluding load
current
VDD = ±4.5 V to ±5.5 V
75
100
75
100
A
VIH = VDD and VIL = GND
VDD = ±2.7 V to ±3.6 V
60
90
60
90
A
VIH = VDD and VIL = GND
IDD for All Power-Down Modes
VIH = VDD and VIL = GND
VDD = ±4.5 V to ±5.5 V
0.5
A
VIH = VDD and VIL = GND
VDD = ±2.7 V to ±3.6 V
0.2
A
VIH = VDD and VIL = GND
POWER EFFICIENCY
IOUT/IDD
96
%
ILOAD = 2 mA and VDD = ±5 V
1
Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.
2
Guaranteed by design and characterization, not production tested.
3
Total current flowing into all pins.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 3.
Parameter
Limit1
Unit
Test Conditions/Comments
t12
33
ns min
SCLK cycle time
t2
5
ns min
SCLK high time
t3
5
ns min
SCLK low time
t4
10
ns min
SYNC to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
4.5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
20
ns min
Minimum SYNC high time
t9
13
ns min
SYNC rising edge to next SCLK falling edge ignored
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 30 MHz.
Figure 2. Timing Diagram
t4
t3
t2
t5
t7
t6
D0
D1
D2
D14
D15
SYNC
SCLK
06853-
002
t9
t1
t8
D15
D14
SDIN
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