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參數(shù)資料
| 型號(hào)： | EVAL-AD5501EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5501 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 16M |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 設(shè)置時(shí)間： | 45µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5501 |
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AD5501
Data Sheet
Rev. C | Page 14 of 20
SELECTING THE OUTPUT RANGE
The output range of the DAC is selected by the R_SEL pin. When
the R_SEL pin is connected to a Logic 1, the DAC output voltage
can be set between 0 V and 30 V. When the R_SEL pin is connected
to a Logic 0, the DAC output voltage can be set between 0 V and
60 V. The state of R_SEL can be changed any time when the serial
interface is not being used, that is, not during a read or write
operation. When the R_SEL pin is changed, the voltage on the
output pin remains the same until the next write to the DAC
register (and LDAC is brought low). For example, if the user
writes 0x800 to the DAC register when in 30 V mode (R_SEL = 1),
the output voltage is 15 V (assuming LDAC is low or has been
pulsed low). When the user switches to 60 V mode (R_SEL = 0),
the output stays at 15 V until the user writes a new value to the
DAC register. LDAC must be low or be pulsed low for the output to
change.
CLR FUNCTION
The AD5501 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive. Bringing the
CLR line low clears the contents of the input register and the DAC
registers to 0x000. The CLR pulse activation time, that is, the falling
edge of CLR to when the output starts to change, is typically 100 ns.
LDAC FUNCTION
The DAC output can be updated using the hardware LDAC pin.
LDAC is normally high. On the falling edge of LDAC, data is
copied from the input register to the DAC register and the DAC
output is updated (asynchronous update mode, see Figure 3). If
the LDAC is kept low or is low on the falling edge of the 16th SCLK,
the DAC register and DAC output are updated automatically
when new data is received in the input register (synchronous
update mode, see Figure 3).
TEMPERATURE SENSOR
The AD5501 has an integrated temperature sensor, which causes
the part to enter thermal shutdown mode when the temperature
on the die exceeds 110°C. In thermal shutdown mode, the analog
section of the device powers down and the DAC output is
disconnected but the digital section remains operational, which
is equivalent to setting the power-down bit in the control register.
To indicate that the AD5501 has entered temperature shutdown
mode, Bit 0 of the control register is set to 1 and the ALARM
pin goes low. The AD5501 remains in temperature shutdown
mode with Bit 0 set to 1 and the ALARM pin low, even if the die
temperature falls, until Bit 0 in the control register is cleared to 0.
POWER DISSIPATION
Drawing current from the VOUT pin causes a temperature rise in
the die and package of the AD5501. The package junction
temperature (TJ) should not exceed 130°C for normal operation. If
the die temperature exceeds 110°C, the AD5501 enters thermal
shutdown mode as described in the previous section. The amount
of heat generated can be calculated using the formula
TJ = TA + (PTOTAL × θJA)
where:
TJ is the package junction temperature.
TA is the ambient temperature.
Absolute Maximum Ratings section for this value).
POWER SUPPLY SEQUENCING
The power supplies for the AD5501 can be applied in any order
without affecting the device. However, before the power supplies
are applied, connect the AGND and DGND pins to the relevant
ground plane. Do not allow any of the digital input pins (SCLK,
SDI, SYNC, R_SEL, and CLR) to float during power up. The
digital input pins can be connected to pull-up (to VLOGIC) or
pull-down (to DGND) resistors as required.
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