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參數(shù)資料
| 型號(hào)： | EVAL-AD5501EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5501 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 16M |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 設(shè)置時(shí)間： | 45µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5501 |
AD5501
Data Sheet
Rev. C | Page 6 of 20
TIMING CHARACTERISTICS
VDD = 30 V, VLOGIC = 2.3 V to 5.5 V, and 40°C < TA < +105°C, all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Limit1
Unit
Test Conditions/Comments
t
1
60
ns min
SCLK cycle time
t
2
10
ns min
SCLK high time
t
3
10
ns min
SCLK low time
t
4
25
ns min
SYNC falling edge to SCLK rising edge setup time
t
5
15
ns min
Data setup time
t
6
5
ns min
Data hold time
t
7
0
ns min
SCLK falling edge to SYNC rising edge
t
8
20
ns min
Minimum SYNC high time
t
9
20
ns min
LDAC pulse width low
t
10
50
ns min
SCLK falling edge to LDAC rising edge
t
11
15
ns min
CLR pulse width low
t
12
100
ns typ
CLR pulse activation time
t
13
20
μs typ
ALARM clear time
t
14
110
ns min
SCLK cycle time in read mode
t
15
55
ns max
SCLK rising edge to SDO valid
t
16
25
ns min
SCLK to SDO Data hold time
t
17
50
μs max
Power-on-reset time (this is not shown in the timing figures)
t
18
50
μs max
Power-on time (this is not shown in the timing figures)
t
19
5
μs typ
ALARM clear to output amplifier turn on (this is not shown in the timing figures)
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 16.667 MHz.
3 Under the load conditions that are outlined in Figure 2.
4 Time from when V
DD or VLOGIC supplies are powered-up to when a digital interface command can be executed.
5 Time required from execution of power-on software command to when the DAC output has settled to 1 V.
Circuit and Timing Diagrams
VOH (MIN) – VOL (MAX)
2
200A
IOL
200A
IOH
TO OUTPUT
PIN
CL
50pF
07992-
002
Figure 2. Load Circuit for SDO Timing Diagram
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