DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 " />
參數(shù)資料
型號(hào): EVAL-AD5380EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 39/40頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD5380
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 40
位數(shù): 14
采樣率(每秒): 125k
數(shù)據(jù)接口: DSP,I²C,MICROWIRE?,并行,QSPI?,SPI?
設(shè)置時(shí)間: 8µs
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: AD5380
AD5380
Data Sheet
Rev. C | Page 8 of 40
TIMING CHARACTERISTICS
SERIAL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.
Table 5.
Parameter1, 2, 3
Limit at T
MIN, TMAX
Unit
Description
t
1
33
ns min
SCLK cycle time
t
2
13
ns min
SCLK high time
t
3
13
ns min
SCLK low time
t
4
13
ns min
SYNC falling edge to SCLK falling edge setup time
13
ns min
24th SCLK falling edge to SYNC falling edge
t
33
ns min
Minimum SYNC low time
t
7
10
ns min
Minimum SYNC high time
t
7A
50
ns min
Minimum SYNC high time in readback mode
t
8
5
ns min
Data setup time
t
9
4.5
ns min
Data hold time
t
30
ns max
24th SCLK falling edge to BUSY falling edge
t
11
670
ns max
BUSY pulse width low (single channel update)
t
20
ns min
24th SCLK falling edge to LDAC falling edge
t
13
20
ns min
LDAC pulse width low
t
14
2
s max
BUSY rising edge to DAC output response time
t
15
0
ns min
BUSY rising edge to LDAC falling edge
t
16
100
ns min
LDAC falling edge to DAC output response time
t
17
8
s typ
DAC output settling time
t
18
20
ns min
CLR pulse width low
t
19
40
s max
CLR pulse activation time
t
20
ns max
SCLK rising edge to SDO valid
t
5
ns min
SCLK falling edge to SYNC rising edge
t
8
ns min
SYNC rising edge to SCLK rising edge
t
23
20
ns min
SYNC rising edge to LDAC falling edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC), and are timed from a voltage level of 1.2 V.
4 Standalone mode only.
5 Daisy-chain mode only.
CL
50pF
TO OUTPUT PIN
VOH (MIN) OR
VOL (MAX)
200
A
200
A
IOL
IOH
03731-002
Figure 2. Load Circuit for Digital Output Timing
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