All input control voltages are specified with t
參數(shù)資料
型號(hào)： EVAL-AD5252EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5252
標(biāo)準(zhǔn)包裝： 1
主要目的： 數(shù)字電位器
已用 IC / 零件： AD5252
主要屬性： 2 通道，256 位置
次要屬性： I²C 接口
已供物品： 板
Data Sheet
AD5251/AD5252
Rev. D | Page 7 of 28
INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both VDD = 3 V and 5 V.
Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts)1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INTERFACE TIMING
SCL Clock Frequency
f
SCL
400
kHz
t
BUF Bus-Free Time Between Stop and Start
t
1
1.3
s
t
HD;STA Hold Time (Repeated Start)
t
2
After this period, the first clock pulse is
generated.
0.6
s
t
LOW Low Period of SCL Clock
t
3
1.3
s
t
HIGH High Period of SCL Clock
t
4
0.6
s
t
SU;STA Set-up Time for Start Condition
t
5
0.6
s
t
HD;DAT Data Hold Time
t
6
0
0.9
s
t
SU;DAT Data Set-up Time
t
7
100
ns
t
F Fall Time of Both SDA and SCL Signals
t
8
300
ns
t
R Rise Time of Both SDA and SCL Signals
t
9
300
ns
t
SU;STO Set-up Time for Stop Condition
t
10
0.6
s
EEMEM Data Storing Time
t
EEMEM_STORE
26
ms
EEMEM Data Restoring Time at Power-On2
t
EEMEM_RESTORE1
V
DD rise time dependent. Measure
without decoupling capacitors at V
DD
and V
SS.
300
s
EEMEM Data Restoring Time upon Restore
Command or Reset Operation2
t
EEMEM_RESTORE2
V
DD = 5 V.
300
s
EEMEM Data Rewritable Time (Delay Time
After Power-On or Reset Before EEMEM
Can Be Written)
t
EEMEM_REWRITE
540
s
FLASH/EE MEMORY RELIABILITY
Endurance3
100
k cycles
Data Retention4
100
Years
1 Guaranteed by design; not subject to production test. See Figure 23 for location of measured values.
2 During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest.
3 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at 40°C, +25°C, and +105°C; typical endurance at +25°C is 700,000
cycles.
4 Retention lifetime equivalent at junction temperature T
J = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature in Flash/EE memory.
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EVAL-AD5254EBZ 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits)
EVAL-AD5254SDZ 功能描述:BOARD EVAL FOR AD5254 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
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