參數(shù)資料
型號(hào)： EVAL-AD1938AZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD1938
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻編解碼器
已用 IC / 零件： AD1938
主要屬性： 24 位，192 kHz，4 ADC: 107dB 動(dòng)態(tài)范圍，8 DAC: 108dB 動(dòng)態(tài)范圍
次要屬性： 分時(shí)復(fù)用（TDM），SPI 接口
已供物品： 板
Data Sheet
AD1938
Rev. E | Page 15 of 32
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1938 is designed for 3.3 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise
pickup. A bulk aluminum electrolytic capacitor of at least 22 μF
should also be provided on the same PCB as the codec. For
critical applications, improved performance is obtained with
separate supplies for the analog and digital sections. If this is
not possible, it is recommended that the analog and digital
supplies be isolated by means of a ferrite bead in series with
each supply. It is important that the analog supply be as clean
as possible.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The ADC and DAC internal voltage reference (VREF) is
brought out on FILTR and should be bypassed as close as
possible to the chip, with a parallel combination of 10 μF and
100 nF. Any external current drawn should be limited to less
than 50 μA.
The internal reference can be disabled in the PLL and Clock
Control 1 register, and FILTR can be driven from an external
source. This configuration can be used to scale the DAC output
to the clipping level of a power amplifier based on its power
supply voltage. The ADC input gain varies by the inverse ratio.
The total gain from ADC input to DAC output remains
constant.
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
The ADC and DAC serial data modes default to I2S. The ports
can also be programmed for left-justified, right-justified, and
TDM modes. The word width is 24 bits by default and can be
programmed for 16 or 20 bits. The DAC serial formats are
programmable according to the DAC Control 0 register. The
polarity of the DBCLK and DLRCLK is programmable according
to DAC Control 1 register. The ADC serial formats and serial
clock polarity are programmable according to ADC Control 1
register. Both DAC and ADC serial ports are programmable to
become the bus masters according to DAC Control 1 register
and ADC Control 2 register. By default, both ADC and DAC
serial ports are in the slave mode.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The AD1938 serial ports also have several different TDM serial
data modes. The first and most commonly used configurations
serial port outputs one data stream consisting of four on-chip
ADCs followed by four unused slots. In Figure 13, the eight
on-chip DAC data slots are packed into one TDM stream. In
this mode, both DBCLK and ABCLK are 256 fS.
The I/O pins of the serial ports are defined according to the
serial mode selected. For a detailed description of the function
of each pin in TDM and auxiliary modes, see Table 12.
The AD1938 allows systems with more than eight DAC channels
to be easily configured by the use of an auxiliary serial data port.
The DAC TDM-AUX mode is shown in Figure 14. In this mode,
the AUX channels are the last four slots of the TDM data stream.
These slots are extracted and output to the AUX serial port. It
should be noted that due to the high DBCLK frequency, this mode
is available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
The AD1938 also allows system configurations with more than
four ADC channels as shown in Figure 15 and Figure 16 that
show using 8 ADCs and 16 ADCs, respectively. Again, due to
the high ABCLK frequency, this mode is available only in the
48 kHz/44.1 kHz/32 kHz sample rate.
Combining the AUX ADC and DAC modes results in a system
configuration of 8 ADCs and 12 DACs. The system, then, con-
sists of two external stereo ADCs, two external stereo DACs,
and one AD1938. This mode is shown in Figure 17 (combined
AUX ADC and DAC modes).
0
558
2-
01
2
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
MSB
MSB–1
MSB–2
DATA
BCLK
LRCLK
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
Figure 12. ADC TDM (8-Channel I2S Mode)
055
82-
0
13
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
MSB
MSB–1
MSB–2
DATA
BCLK
LRCLK
SLOT 5
LEFT 3
SLOT 6
RIGHT 3
SLOT 7
LEFT 4
SLOT 8
RIGHT 4
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
Figure 13. DAC TDM (8-Channel I2S Mode)
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