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| 型號： | EVAL-AD1938AZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1938 |
| 標準包裝： | 1 |
| 主要目的： | 音頻編解碼器 |
| 已用 IC / 零件： | AD1938 |
| 主要屬性： | 24 位，192 kHz，4 ADC: 107dB 動態(tài)范圍，8 DAC: 108dB 動態(tài)范圍 |
| 次要屬性： | 分時復用（TDM），SPI 接口 |
| 已供物品： | 板 |
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Data Sheet
AD1938
Rev. E | Page 19 of 32
DAISY-CHAIN MODE
The AD1938 allows a daisy-chain configuration to expand the
system to 8 ADCs and 16 DACs (see Figure 18). In this mode,
the DBCLK frequency is 512 fS. The first eight slots of the DAC
TDM data stream belong to the first AD1938 in the chain and
the last eight slots belong to the second AD1938. The second
AD1938 is the device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1938 can be configured into a dual-line TDM mode as
shown in Figure 19. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1938 in the chain and the last four channels belong to
the second AD1938.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the AD1938 as shown in Figure 20.
There are two configurations for the ADC port to work in
daisy-chain mode. The first one is with an ABCLK at 256 fS
shown in Figure 21. The second configuration is shown in
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first AD1938 must be grounded in
all modes of operation.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 13 for a detailed description of
the function of each pin. See Figure 26 for a typical AD1938
configuration with two external stereo DACs and two external
stereo ADCs.
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I2S.
05
582
-01
8
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND AD193x
DSDATA2 (TDM_OUT)
OF THE SECOND AD193x
THIS IS THE TDM
TO THE FIRST AD193x
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD193x
FIRST
AD193x
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two-AD1938 Daisy Chain)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1938EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24-Bit CODEC |
| EVAL-AD1938EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR MULTI CHANNEL 96KHZ CODEC - Boxed Product (Development Kits) |
| EVAL-AD1939AZ | 功能描述:BOARD EVAL FOR AD1939 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-AD1939EB | 制造商:Analog Devices 功能描述:EVAL - Bulk |
| EVAL-AD1940AZ | 功能描述:BOARD EVAL AD1940 SIGMADSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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