參數(shù)資料
型號: ET80960JT10016
廠商: Intel
文件頁數(shù): 79/86頁
文件大小: 0K
描述: IC MPU I960JT 3V 100MHZ 132-QFP
標(biāo)準(zhǔn)包裝: 1
處理器類型: i960
特點: 后綴 JT,32 位 16K 高速緩沖
速度: 100MHz
電壓: 3V
安裝類型: 表面貼裝
封裝/外殼: 132-QFP
供應(yīng)商設(shè)備封裝: 132-QFP
包裝: 托盤
其它名稱: 864017
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
80
Datasheet
7.2
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and
HIGHZ pins.
Table 42 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that
contain ‘CTL’ select the direction of bidirectional pins or HIGHZ output pins. When a 1 is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.
Figure 52. Bus States with Arbitration
Ti — IDLE STATE
Ta — ADDRESS STATE
Tw / Td — WAIT/DATA STATE
Tr — RECOVERY STATE
Th — HOLD STATE
To — ONCE STATE
READY — RDYRCV# ASSERTED
NOT READY — RDYRCV# NOT ASSERTED
BURST — BLAST# NOT ASSERTED
NO BURST — BLAST# ASSERTED
RECOVERED — RDYRCV# NOT ASSERTED
NOT RECOVERED — RDYRCV# ASSERTED
REQUEST PENDING — NEW TRANSACTION
NO REQUEST
— NO NEW TRANSACTION
HOLD — HOLD REQUEST ASSERTED
NO HOLD — HOLD REQUEST NOT ASSERTED
LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS
RESET — RESET# ASSERTED
ONCE — ONCE# ASSERTED
Tw/Td
Tr
Th
Ti
Ta
HOLD AND
NOT LOCKED
HOLD
RECOVERED AND
NO REQUEST AND
(NO HOLD OR
LOCKED)
RECOVERED AND
REQUEST
PENDING AND (NO
HOLD OR LOCKED)
NO REQUEST
AND NO HOLD
To
RESET
NOT
RECOVERED
RECOVERED AND
HOLD AND NOT
LOCKED
READY AND NO BURST
(READY AND BURST)
OR NOT READY
REQUEST PENDING
AND (NO HOLD OR
LOCKED)
NO REQUEST
AND (NO HOLD
OR LOCKED)
ONCE & RESET
DEASSERTION
REQUEST
PENDING AND
NO HOLD
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