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參數(shù)資料
| 型號： | ES1371 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ENSONIQ AudioPCI 97 digital controller |
| 中文描述： | ENSONIQ AudioPCI 97數(shù)字控制器 |
| 文件頁數(shù)： | 17/37頁 |
| 文件大小： | 103K |
| 代理商： | ES1371 |
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ENSONIQ Proprietary Information
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
17
Interrupt/Chip Select Status Register
Addressable as longword only
Power on reset value 7FFFFEC0H
Bit(s)
R/W
Name
31
R
INTR
Address 04H
Direct Mapped
Function
This bit is the summary interrupt bit.
0 - No interrupt pending
1 - Interrupt from DAC1, DAC2, ADC, UART, CCB or power
management has occurred.
These bits always read back as ones.
This bit indicates a synchronization error has occurred in the
CODEC interface module.
0 - CODEC synchronization error has not occurred.
1 - CODEC synchronization error has occurred.
These bits are the voice code from the CCB module. These bits are
only valid if the CCB interrupt bit (mccb) is high.
00 - DAC1
01 - DAC2
10 - ADC
11 - Undefined
This bit indicates whether a power level interrupt has occurred.
0 - No Power Level interrupt.
1 - Power Level interrupt pending.
This bit is the masked CCB interrupt bit. A CCB interrupt will occur
if a PCI bus abort condition occurs during a voice buffer transfer.
The CCB interrupt is masked with the CCB interrupt mask bit
(ccb_intrm) in the control register.
0 - No CCB interrupt
1 - CCB interrupt pending
This bit is the UART interrupt bit.
0 - No UART interrupt
1 - UART interrupt pending
This is the DAC1 playback channel interrupt bit.
0 - No DAC1 channel interrupt
1 - DAC1 channel interrupt pending
This is the DAC2 playback channel interrupt bit.
0 - No DAC2 channel interrupt
1 - DAC2 channel interrupt pending
This is the ADC record channel interrupt bit.
0 - No ADC channel interrupt
1 - ADC channel interrupt pending
30:9
8
R
R
ONES
SYNC_ERR
7:6
R
VC[1:0]
5
R
MPWR
4
R
MCCB
3
R
UART
2
R
DAC1
1
R
DAC2
0
R
ADC
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