參數(shù)資料
型號(hào)： ES1371
廠商： Electronic Theatre Controls, Inc.
英文描述： ENSONIQ AudioPCI 97 digital controller
中文描述： ENSONIQ AudioPCI 97數(shù)字控制器
文件頁(yè)數(shù)： 16/37頁(yè)
文件大?。?/td> 103K
代理商： ES1371
ENSONIQ Proprietary Information
ENSONIQ Proprietary Information
ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
16
7
R/W
BREQ
This bit controls access to the internal memory. It is for test
purposes only. If this bit is ever set high it will prevent the CCB,
Serial, UART and HOSTIF modules from accessing the memory.
0 - Memory bus request disabled (power on state)
1 - Memory bus request enabled ( disables memory access )
This bit enables the DAC1 playback channel (CODEC FM DAC).
To restart a channel that had stopped, this bit must be reset low and
then set high.
0 - DAC1 playback channel disabled
1 - DAC1 playback channel enabled
This bit enables the DAC2 playback channel (CODEC DAC).
To restart a channel that had stopped, this bit must be reset low and
then set high.
0 - DAC2 playback channel disabled
1 - DAC2 playback channel enabled
This bit enables the ADC playback channel (CODEC ADC).
To restart a channel that had stopped, this bit must be reset low and
then set high.
0 - ADC record channel disabled
1 - ADC record channel enabled
This bit enables UART module operation.
0 - UART disabled
1 - UART enabled
This bit enables Joystick module operation.
0 - Joystick disabled
1 - Joystick enabled
Xtal Clock Disable. This bit when set high will shut down the
crystal clock input to all internal modules.
0 - Xtal Clock enabled.
1 - Xtal Clock Disabled.
PCI Clock Disable. This bit when set high will shut down the PCI
clock input to all internal modules except the PCI module and the
Interrupt/Chip Select module.
0 - PCI Clock Enabled
1 - PCI Clock Disabled
6
R/W
DAC1_EN
5
R/W
DAC2_EN
4
R/W
ADC_EN
3
R/W
UART_EN
2
R/W
JYSTK_EN
1
R/W
XTALCKDIS
0
R/W
PCICLKDIS
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