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型號(hào): EPM9320BI356-15
文件頁數(shù): 39/42頁
文件大?。?/td> 489K
代理商: EPM9320BI356-15
6
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Figure 1. MAX 9000 Device Block Diagram
Logic Array Blocks
The MAX 9000 architecture is based on linking high-performance, flexible
logic array modules called logic array blocks (LABs). LABs consist of
16-macrocell arrays that are fed by the LAB local array, as shown in
Figure 2 on page 7. Multiple LABs are linked together via the FastTrack
Interconnect, a series of fast, continuous channels that run the entire
length and width of the device. The I/O pins are supported by I/O cells
(IOCs) located at the end of each row (horizontal) and column (vertical)
path of the FastTrack Interconnect.
Each LAB is fed by 33 inputs from the row interconnect and 16 feedback
signals from the macrocells within the LAB. All of these signals are
available within the LAB in their true and inverted form. In addition,
16 shared expander product terms (“expanders”) are available in their
inverted form, for a total of 114 signals that feed each product term in the
LAB. Each LAB is also fed by two low-skew global clocks and one global
clear that can be used for register control signals in all 16 macrocells.
IOC
I/O Cell
(IOC)
Logic Array
Block (LAB)
Macrocell
FastTrack
Interconnect
IOC
LAB Local Array
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EPM9320BI356-20
EPM9320GI280-15
EPM9320GI280-20
EPM9320LC84-15
EPM9320LC84-20
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EPM9320BI356-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
EPM9320GI280-15 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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EPM9320LC84-15 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 320 Macro 60 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM9320LC84-20 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 320 Macro 60 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100