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| 型號： | EPM9320BI356-15 |
| 文件頁數(shù)： | 34/42頁 |
| 文件大?。?/td> | 489K |
| 代理商： | EPM9320BI356-15 |
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Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
All MAX 9000 device packages provide four dedicated inputs for global
control signals with large fan-outs. Each I/O pin has an associated I/O
cell register with a clock enable control on the periphery of the device. As
outputs, these registers provide fast clock-to-output times; as inputs, they
offer quick setup times.
MAX 9000 EPLDs provide 5.0-V in-system programmability (ISP). This
feature allows the devices to be programmed and reprogrammed on the
printed circuit board (PCB) for quick and efficient iterations during design
development and debug cycles. MAX 9000 devices are guaranteed for 100
program and erase cycles.
MAX 9000 EPLDs contain 320 to 560 macrocells that are combined into
groups of 16 macrocells, called logic array blocks (LABs). Each macrocell
has a programmable-AND/fixed-OR array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. For increased flexibility, each macrocell offers a dual-output
structure that allows the register and the product terms to be used
independently. This feature allows register-rich and combinatorial-
intensive designs to be implemented efficiently. The dual-output
structure of the MAX 9000 macrocell also improves logic utilization, thus
increasing the effective capacity of the devices. To build complex logic
functions, each macrocell can be supplemented with both shareable
expander product terms and high-speed parallel expander product terms
to provide up to 32 product terms per macrocell.
The MAX 9000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
user to configure one or more macrocells to operate at 50% or less power
while adding only a nominal timing delay. MAX 9000 devices also
provide an option that reduces the slew rate of the output buffers,
minimizing noise transients when non-speed-critical signals are
switching. MAX 9000 devices offer the MultiVolt feature, which allows
output drivers to be set for either 3.3-V or 5.0-V operation in mixed-
voltage systems.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EPM9320BI356-20 | |
| EPM9320GI280-15 | |
| EPM9320GI280-20 | |
| EPM9320LC84-15 | |
| EPM9320LC84-20 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM9320BI356-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| EPM9320GI280-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| EPM9320GI280-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| EPM9320LC84-15 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 320 Macro 60 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM9320LC84-20 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 320 Macro 60 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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