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| 型號： | EPM7192EQI160-7 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 45/60頁 |
| 文件大?。?/td> | 1030K |
| 代理商： | EPM7192EQI160-7 |
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Altera Corporation
5
MAX 7000A Programmable Logic Device Data Sheet
Notes to tables:
(1)
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or
boundary-scan testing, four I/O pins become JTAG pins.
(2)
All Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM
feature. Therefore, designers can design a board to support a variety of devices,
providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See “SameFrame Pin-
Outs” on page 15 for more details.
(3)
All FineLine BGA packages are footprint-compatible via the SameFrame feature.
Therefore, designers can design a board to support a variety of devices, providing
a flexible migration path across densities and pin counts. Device migration is fully
supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for
more details.
(4)
Altera does not recommend using EPM7128A or EPM7256A devices for new
designs. Use EPM7128AE or EPM7256AE devices for these designs instead.
MAX 7000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000A devices contain from 32 to 512 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms, providing up to 32 product terms
per macrocell.
Table 4. MAX 7000A Maximum User I/O Pins
Device
144-Pin
TQFP
169-Pin
Ultra
FineLine
BGA (2)
208-Pin
PQFP
256-Pin
BGA
256-Pin
FineLine
BGA (3)
EPM7032AE
EPM7064AE
EPM7128A (4)
100
EPM7128AE
100
EPM7256A (4)
120
164
EPM7256AE
120
164
EPM7512AE
120
176
212
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7192QC160-12 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 192-CELL, 12NS PROP DELAY, 160 Pin, Plastic, QFP |
| epm7192qc160-2 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 192-CELL, 20NS PROP DELAY, 160 Pin, Plastic, QFP |
| EPM7192QC160-20 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 192-CELL, 20NS PROP DELAY, 160 Pin, Plastic, QFP |
| EPM7192S | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPM7192SQC160-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 192 Macro 124 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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