參數(shù)資料
型號: EPM7128AETI144-7N
廠商: Altera
文件頁數(shù): 6/64頁
文件大?。?/td> 0K
描述: IC MAX 7000 CPLD 128 144-TQFP
產(chǎn)品變化通告: Bond Wire Change 4/Sept/2008
標準包裝: 180
系列: MAX® 7000A
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 8
宏單元數(shù): 128
門數(shù): 2500
輸入/輸出數(shù): 100
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
包裝: 托盤
其它名稱: 544-2587
EPM7128AETI144-7N-ND
14
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Figure 6. I/O Control Block of MAX 7000A Devices
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to VCC, the output is
enabled.
The MAX 7000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
From
Macrocell
Fast Input to
Macrocell
Register
Slew-Rate Control
To PIA
To Other I/O Pins
6 or 10 Global
Output Enable Signals (1)
PIA
VCC
Open-Drain Output
OE Select Multiplexer
GND
Note:
(1)
EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable
signals. EPM7512AE devices have 10 output enable signals.
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