參數(shù)資料
型號： EPM7128AETI144-7N
廠商： Altera
文件頁數(shù)： 10/64頁
文件大?。?/td> 0K
描述： IC MAX 7000 CPLD 128 144-TQFP
產(chǎn)品變化通告： Bond Wire Change 4/Sept/2008
標(biāo)準(zhǔn)包裝： 180
系列： MAX® 7000A
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 8
宏單元數(shù)： 128
門數(shù)： 2500
輸入/輸出數(shù)： 100
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤
其它名稱： 544-2587
EPM7128AETI144-7N-ND
18
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
A pulse time to erase, program, or read the EEPROM cells.
■
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000A Device
The time required to program a single MAX 7000A device in-system can
be calculated from the following formula:
where: tPROG
= Programming time
tPPULSE
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
CyclePTCK =Number of TCK cycles to program a device
fTCK
= TCK frequency
The ISP times for a stand-alone verification of a single MAX 7000A device
can be calculated from the following formula:
where: tVER
=Verify time
tVPULSE
= Sum of the fixed times to verify the EEPROM cells
CycleVTCK =Number of TCK cycles to verify a device
tPROG
tPPULSE
CyclePTCK
fTCK
--------------------------------
+
=
tVER
tVPULSE
CycleVTCK
fTCK
--------------------------------
+
=
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