f For more information on using " />
參數資料
型號: EPM7032STI44-7N
廠商: Altera
文件頁數: 9/66頁
文件大小: 0K
描述: IC MAX 7000 CPLD 32 44-TQFP
產品變化通告: MAX 7000 Series Obsolescence 08/Jun/2009
標準包裝: 160
系列: MAX® 7000
可編程類型: 系統內可編程
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數目: 2
宏單元數: 32
門數: 600
輸入/輸出數: 36
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應商設備封裝: 44-TQFP(10x10)
包裝: 托盤
其它名稱: 544-2006
EPM7032STI44-7N-ND
Altera Corporation
17
MAX 7000 Programmable Logic Device Family Data Sheet
f For more information on using the Jam language, refer to AN 122: Using
Jam STAPL for ISP & ICR via an Embedded Processor.
The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 7000S device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1.
Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1ms.
2.
Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4.
Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5.
Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6.
Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1ms.
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