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參數(shù)資料
| 型號： | EPL43102 |
| 英文描述： | Graphic STN LCD Drivers with Built-in RAM |
| 中文描述： | 圖形STN液晶顯示器驅(qū)動器，內(nèi)置內(nèi)存 |
| 文件頁數(shù)： | 5/64頁 |
| 文件大?。?/td> | 280K |
| 代理商： | EPL43102 |
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43 COM / 102 SEG LCD DRIVER
The information in this document is subject to change without notice.
8
OSC
I
When using an external oscillator, input the clock to OSC pin.
When using an internal oscillator, leave this pin open.
FRS
O
Static driver output pin.
This pin is used in combination with the FR pin.
IRS
I
Internal resistor select pin.
This pin selects the resistors for adjusting V0 voltage level and is
available only in master mode.
- IRS = "H": The internal resistors are used.
- IRS = "L": The external resistors are used. V0 voltage is controlled
using the external divider resistor connect the VR pin.
MPU INTERFACE
Name
I/O
Description
/RES
I
Hardware reset input.
The LSI is reset when this signal is pulled low. (Active low)
These are the chip select signals. The Chip Select of the LSI
becomes active when CS1 is "L" and also CS2 is "H" and allows the
input/output of data or commands.
/CS1
CS2
Status
“L”
The device is not active. (D7~D0 is Hi-Z)
“L”
“H”
Data and instruction are available.
“H”
“L”
The device is not active. (D7~D0 is Hi-Z)
“H”
The device is not active. (D7~D0 is Hi-Z)
/CS1,CS2
I
A0
I
Used as register selection input.
When A0 = "High", Data register.
When A0 = "Low", Instruction register.
/WR (R/W)
I
When C68 = "High"(68-series MPU interfacing), used as
read (/WR = "High"),write (/WR = "Low")
When C68 = "Low "(80-series MPU interfacing), used as write
enable input (/WR).
/RD (E)
I
When C68 = "High"(68-series MPU interfacing), used as read/write
enable input (E).
When C68 = "Low "(80-series MPU interfacing), used as read enable
input (/RD).
D0 to D7
I/O
When serial mode, D6 (SCK) is used as serial clock input pin, D7
(SDI) is used as serial data input pin, D5 (SDO) is used as serial
data output pin and the others are not used.
When
parallel mode, D0 to D7 are used as bi-directional data bus
pin.
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