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www.semtech.com
HIGH PERFORMANCE PRODUCTS
Revision 1/December 3, 2001
AN1001
IN
IN*
CLK
CLK*
SEL*
SEL
OUT0
OUT0*
OUT1
OUT1*
OUT2
OUT2*
OUT3
OUT3*
OUT4
OUT4*
OUT5
OUT5*
OUT6
OUT6*
OUT7
OUT7*
OUT8
OUT8*
D
D*
Q
Q*
0
1
Asychronous Operation
When used asychronously (SEL = 1), IN is a synchronous
enable and CLK is the input signal. With IN = 1, CLK
passes directly and continuously to all output pins. With
IN = 0, all outputs will transition to a logical 0 (Q = low,
Q* = high) after the next falling edge of CLK. The outputs
will remain low until after a falling edge of CLK while IN =
1. IN is designed to allow signals to be enabled and dis-
abled synchronously, with no glitches or runt pulses at
the output during enable / disable transition time.
The following truth table summarizes the 15XX and 19XX
operation.
SK15XX / 19XX Truth Table
15XX / 19XX Default Condition Chart
Default Conditions
It is good practice to tie all unused inputs to a known,
stable, and a valid voltage level. However, several sig-
nals have internal pull up or pull down resistors and
therefore, have a known state when left floating. The
following chart summarizes the default conditions on the
15XX and 19XX inputs.
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Synchronous Operation (SEL = 0)
Asynchronous Operation
(w / Synchronous Enable) (SEL = 1)
CLK
IN
IN = Synchronous Enable
CLK = Data
OUT <0-8>
OUT <0-4>
OUT <0-8>
OUT <0-4>
CLK
IN
IN = Data
CLK = Clock
SK15XX, SK19XX Functionality (con’d)
SK19XX Functional Block Diagram
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